DS92LX2122SQE National Semiconductor, DS92LX2122SQE Datasheet - Page 10

• Manufacturer Part Number: DS92LX2122SQE
• Description: SERDES, 10-50MHZ, 48LLP
• Manufacturer: National Semiconductor

Specifications of DS92LX2122SQE

• Data Rate: 1.05Gbps
• No. Of Inputs: 1
• No. Of Outputs: 21
• Supply Voltage Range: 1.71V To 1.89V
• Driver Case Style: LLP
• No. Of Pins: 48
• Base Number: 2122
• Operating Temperature Range: -40°C To +85°C
• Serdes Function: Deserializer
• Ic Input Type: LVCMOS
• Ic Output Type: LVCMOS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

www.national.com
I
I
I
I
t
t
t
t
t
t
t
t
t
t
t
t
t
DDR
DDIOR
DDRZ
DDIORZ
TCP
TCIH
TCIL
CLKT
OSC
LHT
HLT
DIS
DIH
PLD
SD
JIND
JINR
Symbol
Recommended Serializer Timing for PCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Serializer Switching Characteristics
Symbol
Symbol
Deserializer (Rx)
VDDn Supply Current
(includes load current)
Deserializer (Rx)
VDDIO Supply Current
(includes load current)
Deserializer (Rx) Supply
Current Power-down
CML Low-to-High
Transition Time
CML High-to-Low
Transition Time
Data Input Setup to PCLK
Data Input Hold from PCLK
Serializer PLL Lock Time
Serializer Delay
Serializer Output
Deterministic Jitter
Serializer Output Random
Jitter
Transmit Clock Period
Transmit Clock Input High
Time
Transmit Clock Input Low
Time
PCLK Input Transition Time
Internal oscillator clock
source
Parameter
Parameter
Parameter
V
CL = 8pF
WORST CASE Pattern
(Figure
V
CL = 8pF
RANDOM Pattern
V
CL = 8pF
WORST CASE Pattern
(Figure
V
CL = 8pF
WORST CASE Pattern
(Figure
PDB = 0V; All other
LVCMOS Inputs = 0V
DDn
DDn
DDIO
DDIO
R
R
(Figure
Serializer Data Inputs
R
RT = 100Ω
f = 10-50 MHz
Reg Address 0x03h b[0] (TRFB = 1)
(Figure
Serializer output intrinsic deterministic
jitter . Measured (cycle-cycle) with
PRBS-7 test pattern PCLK = 50 MHz
Serializer output intrinsic random jitter
(cycle-cycle). Alternating-1,0 pattern.
PCLK = 50 MHz
10 MHz – 50 MHz
(Note
L
L
L
= 1.89V
= 1.89V
= 100Ω
= 100Ω
= 100Ω
= 1.89 V
= 3.6 V
4)
4)
4)
11)
5)
11)
(Figure
Conditions
Conditions
Conditions
5)
10
(Figure
PCLK = 50 MHz
SSCG[3:0] =
ON
Default
Registers
PCLK = 50 MHz
Default
Registers
PCLK = 50 MHz
Default
Registers
PCLK = 50 MHz
Default
Registers
V
V
V
DDn
DDIO
DDIO
9)
= 1.89 V
= 1.89 V
= 3.6 V
6.386T + 5
Min
2.0
2.0
0.4T
0.4T
Min
0.5
20
Min
6.386T +
0.13
0.04
Typ
150
150
12
0.5T
0.5T
1
Typ
25
T
Typ
350
60
53
21
49
42
8
6.386T +
Max
19.7
330
330
0.6T
0.6T
Max
2
100
3
Max
400
800
96
32
83
40
Units
Units
MHz
ms
Units
ps
ps
ns
ns
ns
UI
UI
ns
ns
ns
ns
mA
mA
µA