XC5VLX50-1FFG324C Xilinx Inc, XC5VLX50-1FFG324C Datasheet - Page 339

• Manufacturer Part Number: XC5VLX50-1FFG324C
• Description: FPGA, VIRTEX-5 LX, 50K, 324FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG324C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 1769472
• No. Of I/o's: 220
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 220
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 324-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1562

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
IDELAYCTRL Timing
IDELAYCTRL Locations
Table 7-12
Table 7-12: IDELAYCTRL Switching Characteristics
As shown in
X-Ref Target - Figure 7-16
IDELAYCTRL modules exist in every I/O column in every clock region. An IDELAYCTRL
module calibrates all the IDELAY modules within its clock region. See
Clocks in Chapter 1
Figure 7-17
F
IDELAYCTRL_REF_PRECISION
T
IDELAYCTRLCO_RDY
IDELAYCTRL_REF
REFCLK
shows the IDELAYCTRL switching characteristics.
RST
RDY
illustrates the relative locations of the IDELAYCTRL modules.
Figure
Figure 7-16: Timing Relationship Between RST and RDY
Symbol
7-16, the Virtex-5 FPGA RST is an edge-triggered signal.
for the definition of a clock region.
www.xilinx.com
REFCLK frequency
REFCLK precision
Reset/Startup to Ready for IDELAYCTRL
Input/Output Delay Element (IODELAY)
T
Description
IDELAYCTRLCO_RDY
Global and Regional
ug190_7_11_041206
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