XC6SLX9-2CSG324I Xilinx Inc, XC6SLX9-2CSG324I Datasheet - Page 14

• Manufacturer Part Number: XC6SLX9-2CSG324I
• Description: FPGA, SPARTAN-6 LX, 9K, 324CSGBGA
• Manufacturer: Xilinx Inc
• Series: Spartan® 6 LXr

Specifications of XC6SLX9-2CSG324I

• No. Of Logic Blocks: 1430
• No. Of Macrocells: 9152
• Family Type: Spartan-6
• No. Of Speed Grades: 2
• Total Ram Bits: 589824
• No. Of I/o's: 200
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating: RoHS Compliant
• Number Of Logic Elements/cells: 9152
• Number Of Labs/clbs: 715
• Number Of I /o: 200
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-LFBGA, CSPBGA
• Core Supply Voltage Range: 1.14V To
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 17: GTP Transceiver Clock DC Input Level Specification
GTP Transceiver Switching Characteristics
Consult the Spartan-6 FPGA GTP Transceivers User Guide for further information.
Table 18: GTP Transceiver Performance
Table 19: GTP Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Table 20: GTP Transceiver Reference Clock Switching Characteristics
X-Ref Target - Figure 3
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
F
F
F
F
F
F
F
Symbol
GTPMAX
GTPRANGE1
GTPRANGE2
GTPRANGE3
GPLLMAX
GPLLMIN
GTPDRPCLK
T
T
F
T
T
T
DCREF
PHASE
Symbol
GCLK
LOCK
Symbol
RCLK
FCLK
Symbol
V
C
R
IDIFF
EXT
IN
Reference clock frequency range
Reference clock rise time
Reference clock fall time
Reference clock duty cycle
Clock recovery frequency acquisition
time
Clock recovery phase acquisition time Lock to data after PLL has locked to
GTP transceiver DCLK (DRP clock) maximum frequency
Maximum GTP transceiver data rate
GTP transceiver data rate range when
PLL_TXDIVSEL_OUT = 1
GTP transceiver data rate range when
PLL_TXDIVSEL_OUT = 2
GTP transceiver data rate range when
PLL_TXDIVSEL_OUT = 4
Maximum PLL frequency
Minimum PLL frequency
Differential peak-to-peak input voltage
Differential input resistance
Required external AC coupling capacitor
Description
80%
20%
T
FCLK
Description
Figure 3: Reference Clock Timing Parameters
Description
DC Parameter
20% – 80%
80% – 20%
Transceiver PLL only
Initial PLL lock
the reference clock
T
www.xilinx.com
RCLK
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Conditions
0.94 to 1.62
1.88 to 3.2
0.6 to 0.81
1.62
0.94
3.2
-3
125
0.94 to 1.62
1.88 to 3.2
0.6 to 0.81
-3
Speed Grade
Min
1.62
0.94
60
45
-3N
3.2
–
–
–
–
All LXT Speed Grades
ds162_05_042109
Min
200
Speed Grade
-3N
125
80
–
0.94 to 1.62
Typ
200
200
1.88 to 2.7
0.6 to 0.81
50
–
–
–
1.62
0.94
2.7
Typ
800
100
100
-2
100
-2
Max
160
200
55
–
–
1
2000
Max
120
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-1L
-1L
–
Units
Units
Units
Gb/s
Gb/s
Gb/s
Gb/s
Units
GHz
GHz
MHz
MHz
mV
ms
nF
ps
ps
µs
%

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