MCP1321T-29ME/OT Microchip Technology, MCP1321T-29ME/OT Datasheet - Page 30

• Manufacturer Part Number: MCP1321T-29ME/OT
• Description: Active Low Open-drain + Active High P-P, WDI (WDI = 25.6s, Reset Delay = 200ms,
• Manufacturer: Microchip Technology
• Type: Simple Reset/Power-On Resetr

Specifications of MCP1321T-29ME/OT

• Number Of Voltages Monitored: 1
• Output: Open Drain, Push-Pull
• Reset: Active High/Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 2.9V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-5, SC-74A, SOT-25
• Monitored Voltage: 2 V to 4.7 V
• Undervoltage Threshold: 2.857 V
• Overvoltage Threshold: 2.944 V
• Output Type: Active High, Active Low, Open Drain, Push-Pull
• Manual Reset: Resettable
• Watchdog: Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 2240 ms
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1 V
• Supply Current (typ): 10 uA
• Maximum Power Dissipation: 240 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MCP1321T-29ME/OTTR

MCP131X/2X
4.5
The purpose of the Watchdog Timer (WDT) is to
increase system reliability. The Watchdog Timer fea-
ture can be used to detect when the Host Controller’s
program flow is not as expected. The Watchdog Timer
monitors for activity on the Watchdog Input pin (WDI).
The WDI pin is expected to be strobed within a given
time frame. When this time frame is exceeded, without
an edge transition on the WDI pin, the Reset pin is
driven active to reset the system. This stops the Host
Controller from continuing its erratic behavior (“run-
away” code execution).
The Watchdog Timer is external to the main portion of
the control system and monitors the operation of the
system. This feature is enabled by a falling edge on the
WDI pin (after device POR). Monitoring is then done by
requiring the embedded controller to force an edge
transition (falling or rising) on the WDI pin (“pet the
Watchdog”) within a predetermined time frame (T
If the MCP131X/2X does not detect an edge on the
WDI pin within the expected time frame, the MCP131X/
2X device will force the Reset pin active.
The Watchdog Timer is in the disabled state when:
• The Device Powers up
• A POR event occurred
• A WDT event occurred
• A Manual Reset (MR) event occurred
When the Watchdog Timer is in the disabled state, the
WDI pin has an internal smart pull-up resistor enabled.
This pull-up resistor has a typical value of 52 kΩ. This
pull-up resistor holds the WDI signal in the high state,
until it is forced to another state.
After the embedded controller has initialized, if the
Watchdog Timer feature is to be used, then the embed-
ded controller can force the WDI pin low (V
enables the Watchdog Timer feature and disables the
WDI pull-up resistor.
reduces the device’s current consumption. The pull-up
resistor will remain disconnected until the device has a
power-on, a Reset event occurs, or after the WDT time
out.
Once the Watchdog Timer has been enabled, the Host
Contoller must force an edge transition (falling or rising)
on the WDI pin before the minimum Watchdog Timer
time out to ensure that the Watchdog Timer does not
force the Reset pins (RST/RST) to the active state.
If an edge transition does not occur before the maxi-
mum time out occurs, then the MCP131X/2X will force
the Reset pins to their active state.
The MCP131X/2X supports four time outs. The stan-
dard offering devices have a typical Watchdog Timer
period (T
Watchdog Timer periods. The t
function of the device voltage and temperature.
DS21985B-page 30
Watchdog Timer
WDT
) of 1.6 s.
Disabling the pull-up resistor
Table 4-3
shows the available
WDT
time out is a
IL
). This also
WD
).
Figure 4-19
MCP131X/2X with a PIC
the Watchdog input.
TABLE 4-3:
FIGURE 4-19:
The software routine that strobes WDI is critical. The
code must be in a section of software that is executed
frequently enough so the time between edge transi-
tions is less than the Watchdog time out period. One
common technique controls the Host Controllers I/O
line from two sections of the program. The software
might set the I/O line high while operating in the Fore-
ground mode and set it low while in the Background or
Interrupt modes. If both modes do not execute cor-
rectly, the Watchdog Timer issues reset pulses.
If the time between
Note 1:
WDI edges is less
ensures that the
never forces a
MCP131X/2X
3-Terminal
MCP1700)
(example:
Regulator
than this, it
reset
1.12
17.9
Min
4.3
71
↑
Shaded rows are custom ordered Watch-
dog Timer Periods (t
information on ordering devices with
these t
local Microchip sales office. Minimum
purchase volumes are required.
shows a block diagram for using the
0.1
µF
+5V
WATCHDOG TIMER
PERIODS
WDT
t
WDT
25.6
V
Typ
102
6.3
1.6
Watchdog Timer.
time outs, please contact your
MCP13XX
CC
© 2007 Microchip Technology Inc.
GND
®
microcontroller (MCU) and
WDI
edges is greater
ensures that the
always forces a
between WDI
MCP131X/2X
(1)
than this, it
RST
If the time
WDT
reset
Max
38.4
153
9.3
2.4
+5V
↑
) time outs. For
10 kΩ
MCLR
I/O
MCU
PIC
®
Units
sec
sec
ms
ms