MIC1832NY Micrel Inc, MIC1832NY Datasheet - Page 2
![P Supervisor, 2.88V Or 2.55V VTH, PDIP-08 (Lead-Free)](/photos/7/39/73990/576-8-dip_sml.jpg)
MIC1832NY
Manufacturer Part Number
MIC1832NY
Description
P Supervisor, 2.88V Or 2.55V VTH, PDIP-08 (Lead-Free)
Manufacturer
Micrel Inc
Type
Simple Reset/Power-On Resetr
Datasheet
1.MIC1832MY.pdf
(7 pages)
Specifications of MIC1832NY
Number Of Voltages Monitored
1
Output
Open Drain or Open Collector
Reset
Active High/Active Low
Reset Timeout
250 ms Minimum
Voltage - Threshold
2.55V, 2.88V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
8-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
MIC1832
Pin Configuration
Pin Description
MIC1832
Pin Number
1
2
3
4
5
6
7
8
Pin Name
/PBRST
GND
/RST
RST
TOL
V
/ST
TD
CC
PBRST
GND
TOL
8-Pin SOIC Package
8-Pin PDIP Package
Pin Function
Pushbutton Reset Input: This input is debounced and can be driven with ex-
ternal logic signals or by means of a mechanical pushbutton to actively force
a reset. All pulses less than 1ms in duration on the /PBRST pin are ignored,
whereas, any pulse with a duration of 20ms or greater is guaranteed to
cause a reset.
Time Delay input: This input selects the timebase used by the watchdog
timer. When TD = 0V, the watchdog timeout period is set to a normal value
of 150ms, when TD = open, the watchdog timeout period is et to a nominal
value of 600ms and when TD = V
Tolerance Select Input: Selects whether 5% or 10% of VCC is used as the
reset threshold voltage. When TOL = 0V, the 5% tolerance level is selected
and when TOL = V
IC ground pin, 0V reference
RST is asserted high if either V
dog times out or /PBRST is pulled low for a minimum of 20ms. RST remains
asserted for one reset timeout period after VCC exceeds the reset threshold
or after the watch times out or after /PBRST goes high.
/RST is asserted low if either V
dog times out or /PBRST is pulled low for a minimum of 20ms. /RST remains
asserted for one reset timeout period after V
or after the watch times out or after /PBRST goes high. Open-drain output
Input to watchdog timer. If /ST does not see a transition from high to low
within the watchdog timeout period, RST and /RST will be asserted.
Primary supply input, +5V
TD
1
2
3
4
MIC1832
2
8
7
6
5
CC
V
ST
RST
RST
, a 10% tolerance level is selected.
CC
CC
CC
CC
goes below the reset threshold, the watch-
goes below the reset threshold, the watch-
, the watchdog period is 1.2s nominally.
CC
exceeds the reset threshold
January 2006
Micrel, Inc.