MIC280-4YM6 TR Micrel Inc, MIC280-4YM6 TR Datasheet - Page 8

• Manufacturer Part Number: MIC280-4YM6 TR
• Description: Itty-BittyT Precision Thermal Supervisor -
• Manufacturer: Micrel Inc
• Series: IttyBitty®r

Specifications of MIC280-4YM6 TR

• Function: Temp Monitoring System (Sensor)
• Topology: ADC, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -55°C ~ 125°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-2701-2; MIC280-4YM6 TR; MIC280-4YM6TR; MIC280-4YM6TR

MIC280
(D7) represents the sign: zero for positive temperatures and
one for negative temperatures. Table 3 shows examples of
the data format used by the MIC280 for temperatures:
Extended temperature resolution is provided for the external
zone. The high and low temperature limits and the measured
temperature for zone one are reported as 12-bit values stored
in a pair of 8-bit registers. The measured temperature, for
example, is reported in registers TEMP1h, the high-order byte,
and TEMP1l, the low-order byte. The values in the low-order
bytes are left-justified four-bit binary values representing
one-sixteenth degree increments. The A-D converter resolu-
tion for zone 1 is selectable from nine to twelve bits via the
configuration register. Low-order bits beyond the resolution
selected will be reported as zeroes. Examples of this format
are shown below in Table 4.
FAULT QUEUE
A set of fault queues (programmable digital filters) are pro-
vided in the MIC280 to prevent false tripping due to thermal
or electrical noise. Two bits, CONFIG[5:4], set the depth of
the fault queues. The fault queue setting then determines
the number of consecutive temperature events (TEMPx >
THIGHx or TEMPx < TLOWx) which must occur in order for
the condition to be considered valid. As an example, as-
sume CONFIG[5:4] is programmed with 10b. The measured
temperature for a given zone would have to exceed THIGHx
for four consecutive A/D conversions before /INT would be
asserted or the status bit set.
Like any filter, the fault queue function also has the effect
of delaying the detection of temperature events. In this ex-
ample, it would take 4 x t
The fault queue depth vs. CONFIG[5:4] of the configuration
MIC280
Extended Temperature,
Table 3: Digital Temperature Format, High Bytes
Temperature
+127°C
+125°C
–125°C
–128°C
Low Byte
+25°C
–25°C
+1°C
–1°C
0°C
0.0000
0.0625
0.1250
0.2500
0.5625
0.9375
CONV
0001 1001
0000 0001
0000 0000
1000 0000
1000 0011
0111 1101
1110 0111
0111 1111
1111 1111
Binary
to detect a temperature event.
0000 0000
0000 0000
0000 0000
0000 0000
1000 0000
1000 0000
Binary
Table 4: Digital Temperature Format, Low Bytes
9 BITS
Hex
00
00
00
00
80
80
Hex
7F
7D
FF
E7
19
01
00
83
80
0000 0000
0000 0000
0000 0000
0100 0000
1000 0000
1100 0000
Binary
10 BITS
8
register is shown in Table 5. Note: there is no fault queue
for over-temperature events (CRIT0 and CRIT1) or diode
faults. The fault queue applies only to high-temperature and
low-temperature events as determined by the THIGHx and
TLOWx registers. Any write to CONFIG will result in the fault
queues being purged and reset. Writes to any of the limit
registers, TLOWx or THIGHx, will result in the fault queue for
the corresponding zone being purged and reset.
Interrupt Generation
There are eight different conditions that will cause the MIC280
to set one of the bits in STATUS and assert its /INT output,
if so enabled. These conditions are listed in Table 6. Unlike
previous generations of thermal supervisor IC’s, there are no
interdependencies between any of these conditions. That is,
if CONDITION is true, the MIC280 will respond accordingly,
regardless of any previous or currently pending events.
Normally when a temperature event occurs, the corresponding
status bit will be set in STATUS, the corresponding interrupt
mask bit will be cleared, and /INT will be asserted. Clearing
the interrupt mask bit(s) prohibits continuous interrupt gen-
eration while the device is being serviced. (It is possible to
prevent events from clearing interrupt mask bits by setting
bits in the lock register. See Table 7 for Lockbit function-
ality.) A temperature event will only set bits in the status
register if it is specifically enabled by the corresponding bit
in the interrupt mask register. An interrupt signal will only
be generated on /INT if interrupts are also globally enabled
(IE =1 in CONFIG).
The MIC280 expects to be interrogated using the Alert Re-
sponse Address once it has asserted its interrupt output. Fol-
lowing an interrupt, a successful response to the A.R.A. or a
read operation on STATUS will cause /INT to be de-asserted.
STATUS will also be cleared by the read operation. Reading
STATUS following an interrupt is an acceptable substitute for
Hex
C0
00
00
00
40
80
Resolution
Table 5: Fault Queue Depth Settings
CONFIG[5:4]
0000 0000
0000 0000
0010 0000
0100 0000
1000 0000
1110 0000
00
01
10
11
Binary
11 BITS
Hex
00
00
20
40
80
E0
FAULT QUEUE
1 (Default)
DEPTH
2
4
6
0000 0000
0001 0000
0010 0000
0100 0000
1001 0000
1111 0000
Binary
12 BITS
May 2006
Hex
00
10
20
40
90
F0
Micrel