NCP1392BDR2G ON Semiconductor, NCP1392BDR2G Datasheet
NCP1392BDR2G
Specifications of NCP1392BDR2G
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NCP1392BDR2G Summary of contents
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... Pb−Free Package PINOUT VCC Rt BO GND ORDERING INFORMATION Device Package NCP1392BDR2G SOIC−8 (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1 Publication Order Number: MARKING ...
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Rbo1 AC OUTPUT + PFC FRONT STAGE Cbulk Rbo2 Rf PIN FUNCTION DESCRIPTION Pin # Pin Name Function 1 V Supplies the Driver Timing Resistor 3 BO Brown−Out 4 GND IC Ground 5 Mlower Low−Side Driver Output ...
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ref PFC Delay (100ms ref V DD PON V CC RESET V CC Management V CC Clamp TSD − 0.5ms + Filter + Vref EN − 20ms ...
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MAXIMUM RATINGS TABLE Symbol Vbridge High Voltage Bridge Pin − Pin 6 Vboot − Floating Supply Voltage Vbridge VDRV_HI High−Side Output Voltage VDRV_LO Low−Side Output Voltage dVbridge/dt Allowable Output Slew Rate I Maximum Current that Can Flow into V CC ...
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ELECTRICAL CHARACTERISTICS (For typical values unless otherwise noted) CC Characteristic SUPPLY SECTION Turn−On Threshold Level, V Going Up CC Minimum Operating Voltage after Turn−On Startup Voltage on the Floating Section Cutoff Voltage on the Floating ...
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TEMPERATURE (°C) Figure 3. V CCon 8.85 8.80 8.75 8.70 8.65 8.60 8.55 −40 − TEMPERATURE (°C) Figure 5. ...
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TEMPERATURE (°C) Figure 9. F SWmax 45.0 40.0 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 −40 − TEMPERATURE (°C) Figure ...
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TEMPERATURE (°C) Figure 15. PFC delay 1.015 1.014 1.013 1.012 1.011 1.010 1.009 1.008 1.007 −40 − TEMPERATURE (°C) ...
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The NCP1392 is primarily intended to drive low cost half bridge applications and especially resonant half bridge applications. The IC includes several features that help the designer to cope with resonant SPMS design. ...
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R soft−start soft−start R Delay t Figure 22. The Internal Current Controlled Oscillator Architecture The internal timing capacitor Ct is charged by current which is proportional to the current flowing out from the Rt pin. ...
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Resistor Rfstart together with capacitor C prepares the soft start period after PFC timer SS elapses. The Rt pin is grounded via an internal switch during the PFC delay period to assure that the soft start capacitor ...
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If we decide to turn−on our converter for V and Vref = 1 obtain 5.494 MW upper R = 22.066 kW lower The bridge power dissipation is 400 result confirms our calculations. Figure 25. Simulation ...
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Figure 26. BO Input Functionality − V Figure 27. BO Input Functionality −V http://onsemi.com < V < V bulk2 bulk bulk1 < V < PFC Start Follows bulk2 bulk bulk1 13 ...
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Figure 28. BO Input Functionality − V Figure 29. BO Input Functionality − V Non−Latched Enable Input The non−latched input stops output drivers immediately the BO terminal voltage grows above 2 V threshold. The enable comparator features 100 mV hysteresis ...
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Dimming Q1 Input Figure 30. Dimming Feature Implementation Using Nonlatched Input on BO Terminal The dimming feature can be easily aid to the ballast application by adding two bipolar transistors (Figure 14). ...
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V bulk fstart Voltage Feedback Figure 31. Skip Mode Feature Implementation (Temperature Dependent, Cost Effective Soft−Start After Skip (If Needed Voltage Feedback Q2 R4 ...
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Voltage Feedback IC1 TLV431 R4 Figure 33. Skip Mode Feature Implementation (Better Accuracy) Figures 31 and 33 shows skip implementation using NCP1392 driver. Voltage across resistor R1 (R4) increases when converter ...
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Pulse Trigger DEAD TIME B A from latch high if OK Figure 34. The Internal High−Voltage Section of the NCP1392 The A and B outputs are delivered by the internal logic, as depicted in block diagram. This logic is constructed ...
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... M S *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. The products described herein (NCP1392/D), may be covered by one or more of the following U.S. patents; 6,097, 075; 7176723; 6,362, other patents pending. ...