NCP4303BDR2G ON Semiconductor, NCP4303BDR2G Datasheet - Page 17

• Manufacturer Part Number: NCP4303BDR2G
• Description: SEC SIDE SYNC RECT DRV
• Manufacturer: ON Semiconductor
• Series: -r

Specifications of NCP4303BDR2G

• Applications: Secondary-Side Controller
• Voltage - Input: -
• Voltage - Supply: 10.5 V ~ 30 V
• Current - Supply: -
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Trigger/Disable input
exhibits a typically of 12 ns delay from its activation to the
turn−off of the SR MOSFET. This input offers a possibility
to turn−off the SR MOSFET in applications that operates in
deep CCM via a signal coming from the primary side.
Efficiency and SR performance can be thus further
optimized (refer also to application information on page 12).
The primary trigger signal rising edge should come to the
trigger input before the secondary voltage reverses. Thus the
driver signal for primary switch should be delayed – refer to
figure 46 for one possible method of delaying the primary
The NCP4303 features an ultrafast trigger input that
Figure 38. Recommended Layout for SO8 Package
When Parasitic Inductance Compensation is Used
Figure 40. Trigger Input Internal Connection
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driving signal in CCM flyback topology. The trigger signal
is disabled from the end of the minimum off time period to
the end of the minimum on time period. This technique is
used to:
a) Overcome false turn−off of the gate driver in case the
synchronization pulse is too wide and comes twice per
switching period (in HB and HB LLC applications).
b) Increase trigger input noise immunity against the parasitic
ringing that is present in the SMPS layout during the turn on
process.
Figure 39. Recommended Layout for SO8 Package
When Parasitic Inductance Compensation is Not
Used