PIC12F615-H/MS Microchip Technology, PIC12F615-H/MS Datasheet - Page 27
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PIC12F615-H/MS
Manufacturer Part Number
PIC12F615-H/MS
Description
1.75KB Flash, 64B RAM, 6 I/O, 8MHz Internal Oscillator 8 MSOP 3x3mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Specifications of PIC12F615-H/MS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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3.0
The Flash program memory is readable and writable
during normal operation (full V
is not directly mapped in the register file space.
Instead, it is indirectly addressed through the Special
Function Registers (see Registers 3-1 to 3-5). There
are six SFRs used to read and write this memory:
• PMCON1
• PMCON2
• PMDATL
• PMDATH
• PMADRL
• PMADRH
When interfacing the program memory block, the
PMDATL and PMDATH registers form a two-byte word
which holds the 14-bit data for read/write, and the
PMADRL and PMADRH registers form a two-byte
word which holds the 13-bit address of the Flash loca-
tion being accessed. These devices have 2K words of
program Flash with an address range from 0000h to
07FFh.
The program memory allows single word read and a
by four word write. A four word write automatically
erases the row of the location and writes the new data
(erase before write).
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range
of the device for byte or word operations.
When the device is code-protected, the CPU may
continue to read and write the Flash program memory.
Depending on the settings of the Flash Program
Memory Enable (WRT<1:0>) bits, the device may or
may not be able to write certain blocks of the program
memory, however, reads of the program memory are
allowed.
When the Flash program memory Code Protection
(CP) bit in the Configuration Word register is enabled,
the program memory is code-protected, and the
device programmer (ICSP™) cannot access data or
program memory.
2010 Microchip Technology Inc.
FLASH PROGRAM MEMORY
SELF READ/SELF WRITE
CONTROL (FOR PIC12F617
ONLY)
DD
PIC12F609/615/617/12HV609/615
range). This memory
3.1
The PMADRH and PMADRL registers can address up
to a maximum of 8K words of program memory.
When selecting a program address value, the Most
Significant Byte (MSB) of the address is written to the
PMADRH register and the Least Significant Byte
(LSB) is written to the PMADRL register.
3.2
PMCON1 is the control register for the data program
memory accesses.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental premature
termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear.
PMCON2 is not a physical register. Reading PMCON2
will read all ‘0’s. The PMCON2 register is used
exclusively in the Flash memory write sequence.
PMADRH and PMADRL Registers
PMCON1 and PMCON2 Registers
DS41302D-page 27
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