PIC12F629T-I/MD Microchip Technology, PIC12F629T-I/MD Datasheet - Page 75
PIC12F629T-I/MD
Manufacturer Part Number
PIC12F629T-I/MD
Description
1.75KB Flash, 64 RAM, 6 I/O 8 DFN 4x4mm T/R
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F629T-ISN.pdf
(136 pages)
2.PIC12F629T-ISN.pdf
(8 pages)
3.PIC12F629T-ISN.pdf
(24 pages)
Specifications of PIC12F629T-I/MD
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164326 - MODULA SKT PM3 20QFN
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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DECFSZ
Syntax:
Operands:
Operation:
Status Affected:
Description:
GOTO
Syntax:
Operands:
Operation:
Status Affected:
Description:
INCF
Syntax:
Operands:
Operation:
Status Affected:
Description:
2010 Microchip Technology Inc.
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0 f 127
d [0,1]
(f) - 1 (destination);
skip if result = 0
None
The contents of register ‘f’ are
decremented. If ‘d’ is 0, the result
is placed in the W register. If ‘d’ is
1, the result is placed back in
register ‘f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
then a NOP is executed instead,
making it a 2T
Unconditional Branch
[ label ]
0 k 2047
k PC<10:0>
PCLATH<4:3> PC<12:11>
None
GOTO is an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a two-
cycle instruction.
Increment f
[ label ]
0 f 127
d [0,1]
(f) + 1 (destination)
Z
The contents of register ‘f’ are
incremented. If ‘d’ is 0, the result
is placed in the W register. If ‘d’ is
1, the result is placed back in
register ‘f’.
GOTO k
INCF f,d
CY
instruction.
INCFSZ
Syntax:
Operands:
Operation:
Status Affected:
Description:
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
PIC12F629/675
Increment f, Skip if 0
[ label ]
0 f 127
d [0,1]
(f) + 1 (destination),
None
The contents of register ‘f’ are
incremented. If ‘d’ is 0, the result
is placed in the W register. If ‘d’ is
1, the result is placed back in
register ‘f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
a NOP is executed instead, making
it a 2T
Inclusive OR W with f
[ label ]
0 f 127
d [0,1]
(W) .OR. (f) (destination)
Z
Inclusive OR the W register with
register ‘f’. If ‘d’ is 0, the result is
placed in the W register. If ‘d’ is 1,
the result is placed back in
register ‘f’.
skip if result = 0
Inclusive OR Literal with W
[ label ]
0 k 255
(W) .OR. k (W)
Z
The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
CY
INCFSZ f,d
instruction.
IORWF
IORLW k
DS41190G-page 75
f,d
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