PIC12LF1822-I/P Microchip Technology, PIC12LF1822-I/P Datasheet - Page 90
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PIC12LF1822-I/P
Manufacturer Part Number
PIC12LF1822-I/P
Description
3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Na
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Specifications of PIC12LF1822-I/P
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Processor Series
PIC12LF
Core
PIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12LF1822-I/P
Manufacturer:
MICROCHIP
Quantity:
2 200
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PIC12F/LF1822/PIC16F/LF1823
8.3
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to the
Down Mode (Sleep)”
8.4
The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION register determines on which
edge the interrupt will occur. When the INTEDG bit is
set, the rising edge will cause the interrupt. When the
INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.
8.5
Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the Shadow registers:
• W register
• STATUS register (except for TO and PD)
• BSR register
• FSR registers
• PCLATH register
Upon exiting the Interrupt Service Routine, these regis-
ters are automatically restored. Any modifications to
these registers during the ISR will be lost. If modifica-
tions to any of these registers are desired, the corre-
sponding Shadow register should be modified and the
value will be restored when exiting the ISR. The
Shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s appli-
cation, other registers may also need to be saved.
DS41413B-page 90
Interrupts During Sleep
INT Pin
Automatic Context Saving
for more details.
Section 9.0 “Power-
Preliminary
2010 Microchip Technology Inc.
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