PIC12LF1822T-I/SN Microchip Technology, PIC12LF1822T-I/SN Datasheet - Page 3

• Manufacturer Part Number: PIC12LF1822T-I/SN
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Na
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12LF1822T-I/SN

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: PIC12LF
• Core: PIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Silicon Errata Issues
1. Module: Oscillator
1.1 HS Oscillator
FIGURE 1:
 2010 Microchip Technology Inc.
Note:
F
T
T
See the ADC Clock Period (T
section of the DS41413B data sheet.
The HS oscillator requires a minimum voltage of
3.0 volts (at 65°C or less) to operate at 20 MHz.
Work around
None.
Affected Silicon Revisions
CY
AD
OSC
A6
X
= 4/32 MHz = 125 nsec
= 1 µsec, ADCS = F
= 32 MHz
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A8).
4 T
A8
8 T
1 T
CY
CY
AD
INSTRUCTION CYCLE DELAY CALCULATION EXAMPLE
OSC
/32
AD
) vs. Device Operating Frequencies table, in the Analog-to-Digital Converter
88 T
PIC12(L)F1822/PIC16(L)F1823
11 T
84 T
CY
AD
CY
2. Module: ADC
2.1 Analog-to-Digital Converter (ADC)
Under certain device operating conditions, the
ADC conversion may not complete properly. When
this occurs, the ADC Interrupt Flag (ADIF) does
not get set, the GO/DONE bit does not get cleared
and the conversion result does not get loaded into
the ADRESH and ADRESL result registers.
Work around
Method 1: Select
Method 2: Provide a fixed delay in software
oscillator as the ADC conversion
clock source, and perform all
conversions with the device in
Sleep.
to stop the A-to-D conversion
manually, after all 10 bits are
converted,
conversion
automatically. The conversion is
stopped by clearing the GO/
DONE bit in software. The GO/
DONE bit must be cleared during
the last ½ T
conversion
completed automatically. Refer to
Figure 1
Stop the A/D conversion
between 10.5 and 11 T
cycles.
See the Analog-to-Digital
Conversion Timing diagram
in
Converter section of the
DS41413B data sheet.
the
for details.
the
AD
Analog-to-Digital
but
would
cycle, before the
DS80502B-page 3
dedicated
would
before
complete
AD
have
RC
the