PIC12LF1840-E/P Microchip Technology, PIC12LF1840-E/P Datasheet - Page 110
![7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano](/photos/16/3/160349/pdip8_sml.jpg)
PIC12LF1840-E/P
Manufacturer Part Number
PIC12LF1840-E/P
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Datasheet
1.PIC12F1840-EMF.pdf
(382 pages)
Specifications of PIC12LF1840-E/P
Processor Series
PIC12F
Core
PIC
Program Memory Type
Flash
Program Memory Size
7 KB
Data Ram Size
256 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Package / Case
PDIP-8
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Core Processor
RISC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
Details
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PIC12(L)F1840
REGISTER 11-6:
TABLE 11-3:
DS41441B-page 110
EECON1
EECON2
EEADRL
EEADRH
EEDATL
EEDATH
INTCON
PIE2
PIR2
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Data EEPROM module.
bit 7
Legend:
R = Readable bit
S = Bit can only be set
‘1’ = Bit is set
bit 7-0
Name
W-0/0
*
Page provides register information.
EEPGD
OSFIE
OSFIF
Bit 7
GIE
—
—
Data EEPROM Unlock Pattern bits
To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
EECON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes. Refer to
Memory”
SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM
W-0/0
EECON2: EEPROM CONTROL 2 REGISTER
CFGS
PEIE
Bit 6
for more information.
—
—
—
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
EEPROM Control Register 2 (not a physical register)
W-0/0
TMR0IE
LWLO
Bit 5
C1IE
C1IF
EEPROM Control Register 2
W-0/0
FREE
Bit 4
INTE
EEIE
EEIF
Preliminary
EEADRL<7:0>
EEDATL<7:0>
EEADRH<6:0
WRERR
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
BCL1IE
BCL1IF
IOCIE
Bit 3
EEDATH<5:0>
W-0/0
Section 11.2.2 “Writing to the Data EEPROM
TMR0IF
WREN
Bit 2
—
—
W-0/0
Bit 1
INTF
WR
—
—
2011 Microchip Technology Inc.
W-0/0
IOCIF
Bit 0
RD
—
—
Register
on Page
W-0/0
110*
109
108
108
108
108
83
85
87
bit 0
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