PIC12LF1840T-I/MF Microchip Technology, PIC12LF1840T-I/MF Datasheet - Page 320
![7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano](/photos/16/0/160077/dfn8_sml.jpg)
PIC12LF1840T-I/MF
Manufacturer Part Number
PIC12LF1840T-I/MF
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Datasheet
1.PIC12F1840-EMF.pdf
(382 pages)
Specifications of PIC12LF1840T-I/MF
Processor Series
PIC12F
Core
PIC
Program Memory Type
Flash
Program Memory Size
7 KB
Data Ram Size
256 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
DFN-8
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Core Processor
RISC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12LF1840T-I/MF
Manufacturer:
MICROCHIP
Quantity:
12 000
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PIC12(L)F1840
SWAPF
Syntax:
Operands:
Operation:
Status Affected:
Description:
TRIS
Syntax:
Operands:
Operation:
Status Affected:
Description:
DS41441B-page 320
Swap Nibbles in f
[ label ]
0 f 127
d [0,1]
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
None
The upper and lower nibbles of regis-
ter ‘f’ are exchanged. If ‘d’ is ‘0’, the
result is placed in the W register. If ‘d’
is ‘1’, the result is placed in register ‘f’.
Load TRIS Register with W
[ label ] TRIS f
5 f 7
(W) TRIS register ‘f’
None
Move data from W register to TRIS
register.
When ‘f’ = 5, TRISA is loaded.
When ‘f’ = 6, TRISB is loaded.
When ‘f’ = 7, TRISC is loaded.
SWAPF f,d
Preliminary
XORLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
XORWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Exclusive OR W with f
[ label ]
0 f 127
d [0,1]
(W) .XOR. (f) destination)
Z
Exclusive OR the contents of the W
register with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in regis-
ter ‘f’.
Exclusive OR literal with W
[ label ]
0 k 255
(W) .XOR. k W)
Z
The contents of the W register are
XOR’ed with the eight-bit
literal ‘k’. The result is placed in the
W register.
2011 Microchip Technology Inc.
XORWF
XORLW k
f,d
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