PIC16F1507T-I/ML Microchip Technology, PIC16F1507T-I/ML Datasheet - Page 21

• Manufacturer Part Number: PIC16F1507T-I/ML
• Description: 3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 QFN 4x4mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F1507T-I/ML

• Processor Series: PIC16
• Core: PIC16F
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 3.5 KB
• Data Ram Size: 128 B
• Interface Type: ICSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 3
• Operating Supply Voltage: 2.3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-20
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 30 uA
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: -
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: -
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / Rohs Status: Details

TABLE 3-3:
Legend:
40Bh
40Ch
40Dh
40Eh
41Ah
41Bh
41Ch
41Dh
41Eh
80Bh
80Ch
400h
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Fh
420h
46Fh
470h
47Fh
800h
86Fh
870h
87Fh
Unimplemented
Unimplemented
Core Registers
Common RAM
Core Registers
Common RAM
Read as ‘0’
Read as ‘0’
(Table
70h – 7Fh)
BANK 16
(Table
70h – 7Fh)
(Accesses
(Accesses
BANK 8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
= Unimplemented data memory locations, read as ‘0’
3-2)
3-2)
PIC16(L)F1507 MEMORY MAP (CONTINUED)
48Bh
48Ch
48Dh
48Eh
49Ah
49Bh
49Ch
49Dh
49Eh
4A0h
4EFh
4FFh
88Bh
88Ch
8EFh
8FFh
480h
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Fh
4F0h
880h
8F0h
Unimplemented
Unimplemented
Core Registers
Core Registers
Common RAM
Common RAM
NCO1ACCH
NCO1ACCU
NCO1ACCL
NCO1INCH
NCO1INCL
NCO1CON
Read as ‘0’
BANK 17
Read as ‘0’
(Table
NCO1CLK
70h – 7Fh)
(Table
70h – 7Fh)
(Accesses
(Accesses
BANK 9
—
—
—
—
—
—
—
—
—
—
—
—
—
3-2)
3-2)
50Bh
50Ch
50Dh
50Eh
51Ah
51Bh
51Ch
51Dh
51Eh
90Bh
90Ch
97Fh
500h
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Fh
520h
56Fh
570h
57Fh
900h
96Fh
970h
Unimplemented
Unimplemented
Core Registers
Core Registers
Common RAM
Common RAM
BANK 10
Read as ‘0’
70h – 7Fh)
BANK 18
Read as ‘0’
70h – 7Fh)
(Table
(Table
(Accesses
(Accesses
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3-2)
3-2)
58Bh
58Ch
58Dh
58Eh
58Fh
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
5EFh
5F0h
5FFh
98Bh
98Ch
9EFh
9F0h
9FFh
580h
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
980h
Unimplemented
Unimplemented
Core Registers
Core Registers
Common RAM
Common RAM
Read as ‘0’
Read as ‘0’
70h – 7Fh)
BANK 19
70h – 7Fh)
BANK 11
(Table
(Accesses
(Table
(Accesses
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3-2)
3-2)
A0Ch
60Bh
60Ch
60Dh
60Eh
60Fh
61Ah
61Bh
61Ch
61Dh
61Eh
61Fh
64Fh
67Fh
A00h
A0Bh
A6Fh
A70h
A7Fh
600h
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
620h
650h
Unimplemented
Unimplemented
Core Registers
Core Registers
Common RAM
Common RAM
PWM1DCH
PWM1CON
PWM2DCH
PWM2CON
PWM3DCH
PWM3CON
PWM4DCH
PWM4CON
Read as ‘0’
Read as ‘0’
BANK 12
PWM1DCL
PWM2DCL
PWM3DCL
PWM4DCL
70h – 7Fh)
BANK 20
70h – 7Fh)
(Table
(Accesses
(Table
(Accesses
—
—
—
—
—
—
—
—
3-2)
3-2)
A8Bh
A8Ch
AEFh
AFFh
68Bh
68Ch
68Dh
68Eh
68Fh
692h
694h
695h
69Ah
69Bh
69Ch
69Dh
69Eh
69Fh
6A0h
6EFh
6F0h
6FFh
A80h
AF0h
680h
690h
691h
693h
696h
697h
698h
699h
Unimplemented
Unimplemented
Core Registers
Core Registers
Common RAM
Common RAM
CWG1CON0
CWG1CON1
CWG1CON2
CWG1DBR
Read as ‘0’
Read as ‘0’
BANK 13
(Table
CWG1DBF
70h – 7Fh)
BANK 21
(Table
70h – 7Fh)
(Accesses
(Accesses
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3-2)
3-2)
B0Bh
B0Ch
700h
70Bh
70Ch
70Dh
70Eh
70Fh
710h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
71Fh
720h
76Fh
770h
77Fh
B00h
B6Fh
B70h
B7Fh
711h
Unimplemented
Unimplemented
Core Registers
Common RAM
Core Registers
Common RAM
Read as ‘0’
Read as ‘0’
BANK 14
(Table
70h – 7Fh)
BANK 22
(Table
70h – 7Fh)
(Accesses
(Accesses
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3-2)
3-2)
B8Bh
B8Ch
BEFh
BFFh
780h
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
7EFh
7F0h
7FFh
B80h
BF0h
Unimplemented
Unimplemented
Core Registers
Common RAM
Core Registers
Common RAM
Read as ‘0’
Read as ‘0’
BANK 15
(Table
70h – 7Fh)
BANK 23
(Table
70h – 7Fh)
(Accesses
(Accesses
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3-2)
3-2)