PIC16F505T-I/MG Microchip Technology, PIC16F505T-I/MG Datasheet - Page 37
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PIC16F505T-I/MG
Manufacturer Part Number
PIC16F505T-I/MG
Description
1.5 KB Flash, 72 RAM, 12 I/O 16 QFN 3x3x0.9mm T/R
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC12F509T-ISN.pdf
(110 pages)
Specifications of PIC16F505T-I/MG
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
11
Program Memory Size
1.5KB (1K x 12)
Program Memory Type
FLASH
Ram Size
72 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
6.1
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock require-
ment is due to internal phase clock (T
zation. Also, there is a delay in the actual incrementing
of Timer0 after synchronization.
6.1.1
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 6-4).
Therefore, it is necessary for T0CKI to be high for at
least 2 T
for at least 2 T
Refer to the electrical specification of the desired
device.
FIGURE 6-4:
© 2009 Microchip Technology Inc.
Note 1: Delay from clock input change to Timer0 increment is 3 T
External Clock/Prescaler
OSC
External Clock Input or
Increment Timer0 (Q4)
Using Timer0 with an External
Clock
Output After Sampling
2: External clock if no prescaler selected; prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
Prescaler Output
EXTERNAL CLOCK
SYNCHRONIZATION
(and a small RC delay of 2 Tt0H) and low
in measuring the interval between two edges on Timer0 input = ±4 T
OSC
(and a small RC delay of 2 Tt0H).
TIMER0 TIMING WITH EXTERNAL CLOCK
Timer0
(2)
Q1 Q2 Q3 Q4
(3)
OSC
) synchroni-
(1)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T0
PIC12F508/509/16F505
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler, so that the prescaler output is symmetrical.
For the external clock to meet the sampling require-
ment, the ripple counter must be taken into account.
Therefore, it is necessary for T0CKI to have a period of
at least 4 T
divided by the prescaler value. The only requirement
on T0CKI high and low time is that they do not violate
the minimum pulse width requirement of Tt0H. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device.
6.1.2
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-4 shows the
delay from the external clock edge to the timer
incrementing.
OSC
to 7 T
OSC
T0 + 1
OSC
TIMER0 INCREMENT DELAY
OSC
. (Duration of Q = T
max.
(and a small RC delay of 4 Tt0H)
OSC
T0 + 2
Small pulse
misses sampling
). Therefore, the error
DS41236E-page 37