PIC16F616-H/ML Microchip Technology, PIC16F616-H/ML Datasheet - Page 22

• Manufacturer Part Number: PIC16F616-H/ML
• Description: 1.75KB Flash, 64B RAM, 6 I/O, 8MHz Internal Oscillator 16 QFN 4x4mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F616-H/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 11
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 16-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F610/616/16HV610/616
2.2.2.5
The PIR1 register contains the peripheral interrupt flag
bits, as shown in Register 2-5.
REGISTER 2-5:
DS41288F-page 22
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
U-0
—
PIC16F616/16HV616 only. PIC16F610/16HV610 unimplemented, read as ‘0’.
PIR1 Register
Unimplemented: Read as ‘0’
ADIF: A/D Interrupt Flag bit
1 = A/D conversion complete
0 = A/D conversion has not completed or has not been started
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
C2IF: Comparator C2 Interrupt Flag bit
1 = Comparator C2 output has changed (must be cleared in software)
0 = Comparator C2 output has not changed
C1IF: Comparator C1 Interrupt Flag bit
1 = Comparator C1 output has changed (must be cleared in software)
0 = Comparator C1 output has not changed
Unimplemented: Read as ‘0’
TMR2IF: Timer2 to PR2 Match Interrupt Flag bit
1 = Timer2 to PR2 match occurred (must be cleared in software)
0 = Timer2 to PR2 match has not occurred
TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = Timer1 register overflowed (must be cleared in software)
0 = Timer1 has not overflowed
ADIF
R/W-0
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
(1)
W = Writable bit
‘1’ = Bit is set
CCP1IF
R/W-0
(1)
(1)
R/W-0
(1)
C2IF
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
C1IF
(1)
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register. User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
U-0
—
© 2009 Microchip Technology Inc.
x = Bit is unknown
TMR2IF
R/W-0
(1)
TMR1IF
R/W-0
bit 0