PIC16F723A-E/ML Microchip Technology, PIC16F723A-E/ML Datasheet - Page 140

• Manufacturer Part Number: PIC16F723A-E/ML
• Description: 7 KB Flash, 1.8V-5.5V, 16 MHz Int. Osc. 28 QFN 6x6mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F723A-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF722A/723A
16.1.2.8
1.
2.
3.
4.
5.
6.
7.
8.
9.
FIGURE 16-5:
DS41417A-page 140
Initialize the SPBRG register and the BRGH bit
to achieve the desired baud rate (refer to
Section 16.2 “AUSART Baud Rate Generator
(BRG)”).
Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Enable reception by setting the CREN bit.
The RCIF interrupt flag bit of the PIR1 register
will be set when a character is transferred from
the RSR to the receive buffer. An interrupt will be
generated if the RCIE bit of the PIE1 register
was also set.
Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register.
If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
Note:
RX/DT pin
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Asynchronous Reception Set-up:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
Start
ASYNCHRONOUS RECEPTION
bit
bit 0
bit 1
bit 7/8
Stop
bit
Word 1
RCREG
Start
bit
bit 0
16.1.2.9
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If an overrun occurred, clear the OERR flag by
11. If the device has been addressed, clear the
Initialize the SPBRG register and the BRGH bit
to achieve the desired baud rate (refer to
Section 16.2 “AUSART Baud Rate Generator
(BRG)”).
Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
Enable 9-bit reception by setting the RX9 bit.
Enable address detection by setting the ADDEN
bit.
Enable reception by setting the CREN bit.
The RCIF interrupt flag bit of the PIR1 register
will be set when a character with the ninth bit set
is transferred from the RSR to the receive buffer.
An interrupt will be generated if the RCIE inter-
rupt enable bit of the PIE1 register was also set.
Read the RCSTA register to get the error flags.
The ninth data bit will always be set.
Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
clearing the CREN receiver enable bit.
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
bit 7/8 Stop
Word 2
RCREG
9-bit Address Detection Mode Set-up
bit
Start
 2010 Microchip Technology Inc.
bit
bit 7/8
Stop
bit