PIC16F723A-E/MV Microchip Technology, PIC16F723A-E/MV Datasheet - Page 174
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PIC16F723A-E/MV
Manufacturer Part Number
PIC16F723A-E/MV
Description
7 KB Flash, 1.8V-5.5V, 16 MHz Int. Osc. 28 UQFN 4x4x0.5mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16F722AT-ISS.pdf
(284 pages)
Specifications of PIC16F723A-E/MV
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-UFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16F/LF722A/723A
REGISTER 17-3:
DS41417A-page 174
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1: When this mode is selected, any reads or writes to the SSPADD SFR address accesses the SSPMSK register.
WCOL
R/W-0
2: When enabled, these pins must be properly configured as input or output using the associated TRIS bit.
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
0 = No collision
SSPOV: Receive Overflow Indicator bit
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
1 = Release control of SCL
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
SSPM<3:0>: Synchronous Serial Port Mode Select bits
0110 = I
0111 = I
1000 = Reserved
1001 = Load SSPMSK register at SSPADD SFR Address
1010 = Reserved
1011 = I
1100 = Reserved
1101 = Reserved
1110 = I
1111 = I
SSPOV
R/W-0
software)
care” in Transmit mode. SSPOV must be cleared in software in either mode.
SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER (I
2
2
2
2
2
C Slave mode, 7-bit address
C Slave mode, 10-bit address
C Firmware Controlled Master mode (Slave Idle)
C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
R/W-0
CKP
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPM3
R/W-0
(1)
SSPM2
R/W-0
2010 Microchip Technology Inc.
x = Bit is unknown
SSPM1
R/W-0
(2)
2
C MODE)
SSPM0
R/W-0
bit 0
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