PIC16LF1507-E/P Microchip Technology, PIC16LF1507-E/P Datasheet - Page 86

3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 PDIP .300in TUBE

PIC16LF1507-E/P

Manufacturer Part Number
PIC16LF1507-E/P
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 PDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet

Specifications of PIC16LF1507-E/P

Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Package / Case
PDIP-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
 Details
10.2.2
The unlock sequence is a mechanism that protects the
Flash program memory from unintended self-write pro-
gramming or erasing. The sequence must be executed
and completed without interruption to successfully
complete any of the following operations:
• Row Erase
• Load program memory write latches
• Write of program memory write latches to pro-
• Write of program memory write latches to User
The unlock sequence consists of the following steps:
1. Write 55h to PMCON2
2. Write AAh to PMCON2
3. Set the WR bit in PMCON1
4. NOP instruction
5. NOP instruction
Once the WR bit is set, the processor will always force
two NOP instructions. When an Erase Row or Program
Row operation is being performed, the processor will stall
internal operations (typical 2 ms), until the operation is
complete and then resume with the next instruction.
When the operation is loading the program memory write
latches, the processor will always force the two NOP
instructions and continue uninterrupted with the next
instruction.
Since the unlock sequence must not be interrupted,
global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is
completed.
 2011 Microchip Technology Inc.
gram memory
IDs
FLASH MEMORY UNLOCK
SEQUENCE
Preliminary
FIGURE 10-3:
Instruction Fetched ignored
Instruction Fetched ignored
PIC16(L)F1507
Write or Erase operation
NOP execution forced
NOP execution forced
Unlock Sequence
Unlock Sequence
Write 0AAh to
Write 055h to
FLASH PROGRAM
MEMORY UNLOCK
SEQUENCE FLOWCHART
PMCON2
PMCON2
(WR = 1)
Initiate
Start
End
DS41586A-page 86

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