PIC16LF1507-E/SO Microchip Technology, PIC16LF1507-E/SO Datasheet - Page 213

3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 SOIC .300in TUBE

PIC16LF1507-E/SO

Manufacturer Part Number
PIC16LF1507-E/SO
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet

Specifications of PIC16LF1507-E/SO

Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOIC-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
 Details
PIC16(L)F1507
CALL
Syntax:
Operands:
Operation:
Status Affected:
Description:
CALLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
CLRF
Syntax:
Operands:
Operation:
Status Affected:
Description:
CLRW
Syntax:
Operands:
Operation:
Status Affected:
Description:
DS41586A-page 213
Call Subroutine
[ label ] CALL k
0  k  2047
(PC)+ 1  TOS,
k  PC<10:0>,
(PCLATH<4:3>)  PC<12:11>
None
Call Subroutine. First, return address
(PC + 1) is pushed onto the stack.
The eleven-bit immediate address is
loaded into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALL is a two-cycle instruc-
tion.
Clear W
[ label ] CLRW
None
00h  (W)
1  Z
Z
W register is cleared. Zero bit (Z) is
set.
Subroutine Call With W
[ label ] CALLW
None
(PC) +1  TOS,
(W)  PC<7:0>,
(PCLATH<6:0>)  PC<14:8>
None
Subroutine call with W. First, the
return address (PC + 1) is pushed
onto the return stack. Then, the con-
tents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLW is a two-cycle
instruction.
Clear f
[ label ] CLRF
0  f  127
00h  (f)
1  Z
Z
The contents of register ‘f’ are cleared
and the Z bit is set.
f
Preliminary
CLRWDT
Syntax:
Operands:
Operation:
Status Affected:
Description:
COMF
Syntax:
Operands:
Operation:
Status Affected:
Description:
DECF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Complement f
(f)  (destination)
[ label ] COMF
0  f  127
d  [ 0 , 1 ]
Z
The contents of register ‘f’ are com-
plemented. If ‘d’ is ‘ 0 ’, the result is
stored in W. If ‘d’ is ‘ 1 ’, the result is
stored back in register ‘f’.
Decrement f
[ label ] DECF f,d
0  f  127
d  [ 0 , 1 ]
(f) - 1  (destination)
Z
Decrement register ‘f’. If ‘d’ is ‘ 0 ’, the
result is stored in the W
register. If ‘d’ is ‘ 1 ’, the result is stored
back in register ‘f’.
Clear Watchdog Timer
[ label ] CLRWDT
None
00h  WDT
0  WDT prescaler,
1  TO
1  PD
TO, PD
CLRWDT instruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT.
Status bits TO and PD are set.
 2011 Microchip Technology Inc.
f,d

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