PIC16LF1826-E/P Microchip Technology, PIC16LF1826-E/P Datasheet - Page 237
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PIC16LF1826-E/P
Manufacturer Part Number
PIC16LF1826-E/P
Description
18 Pin, 3.5 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16F1826-IP.pdf
(406 pages)
Specifications of PIC16LF1826-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
PIC16LF
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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FIGURE 24-4:
24.2.1
The MSSPx module has five registers for SPI mode
operation. These are:
• MSSPx STATUS register (SSPxSTAT)
• MSSPx Control Register 1 (SSPxCON1)
• MSSPx Control Register 3 (SSPxCON3)
• MSSPx Data Buffer register (SSPxBUF)
• MSSPx Address register (SSPxADD)
• MSSPx Shift register (SSPxSR)
SSPxCON1 and SSPxSTAT are the control and STA-
TUS registers in SPI mode operation. The SSPxCON1
register is readable and writable. The lower 6 bits of
the SSPxSTAT are read-only. The upper two bits of the
SSPxSTAT are read/write.
In one SPI master mode, SSPxADD can be loaded
with a value used in the Baud Rate Generator. More
information on the Baud Rate Generator is available in
Section 24.7 “Baud Rate Generator”.
SSPxSR is the shift register used for shifting data in
and out. SSPxBUF provides indirect access to the
SSPxSR register. SSPxBUF is the buffer register to
which data bytes are written, and from which data
bytes are read.
In receive operations, SSPxSR and SSPxBUF
together create a buffered receiver. When SSPxSR
receives a complete byte, it is transferred to SSPxBUF
and the SSPxIF interrupt is set.
During transmission, the SSPxBUF is not buffered. A
write to SSPxBUF will write to both SSPxBUF and
SSPxSR.
2010 Microchip Technology Inc.
(Not directly accessible)
SPI MODE REGISTERS
SPI Master
SPI MASTER AND MULTIPLE SLAVE CONNECTION
General I/O
General I/O
General I/O
SDOx
SCKx
SDIx
Preliminary
PIC16F/LF1826/27
SCKx
SDIx
SDOx
SSx
SCKx
SDIx
SDOx
SSx
SCKx
SDIx
SDOx
SSx
SPI Slave
SPI Slave
SPI Slave
#1
#2
#3
DS41391C-page 237
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