PIC16LF1902-E/SP Microchip Technology, PIC16LF1902-E/SP Datasheet
PIC16LF1902-E/SP
Specifications of PIC16LF1902-E/SP
Related parts for PIC16LF1902-E/SP
PIC16LF1902-E/SP Summary of contents
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... LCD Driver and nanoWatt XLP Technology 2011 Microchip Technology Inc. PIC16LF1902/3 Data Sheet 28-Pin Flash-Based, 8-Bit CMOS Microcontrollers with Preliminary DS41455B ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Programmable Code Protection • Power-Saving Sleep mode 2011 Microchip Technology Inc. PIC16LF1902/3 Extreme Low-Power Management PIC16LF1902/3 with nanoWatt XLP: • Sleep mode 1.8V, typical • Watchdog Timer: 300 nA @ 1.8V, typical • Timer1 Oscillator: 500 nA @ 1.8V, typical Analog Features: • Analog-to-Digital Converter (ADC): ...
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... PIC16LF1902/3 Family Types Device PIC16LF1902 2048 PIC16LF1903 4096 COM3 and SEG15 share a pin, so the total segments are limited to 72 for 28-pin devices. Note 1: FIGURE 1: 28-PIN PDIP, SOIC, SSOP PACKAGE DIAGRAM FOR PIC16LF1902/3 28-Pin PDIP, SOIC, SSOP V /MCLR/RE3 PP SEG12/AN0/RA0 SEG7/AN1/RA1 COM2/AN2/RA2 SEG15/COM3/V ...
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... FIGURE 2: 28-PIN UQFN PACKAGE DIAGRAM FOR PIC16LF1902/3 28-Pin UQFN COM2/AN2/RA2 SEG15/COM3/V +/AN3/RA3 REF SEG4/T0CKI/RA4 SEG5/AN4/RA5 V SS SEG2/CLKIN/RA7 SEG1/CLKOUT/RA6 These pins have interrupt-on-change functionality. Note 1: 2011 Microchip Technology Inc. PIC16LF1902/3 RB3 1 21 RB2 RB1 19 PIC16LF1902/3 4 RB0 RC7/SEG8 7 15 Preliminary (1) /AN9/SEG26/VLCD3 (1) /AN8/SEG25/VLCD2 ...
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... PIC16LF1902/3 TABLE 1: 28-PIN ALLOCATION TABLE (PIC16LF1902/3) RA0 2 27 AN0 RA1 3 28 AN1 RA2 4 1 AN2 RA3 5 2 AN3/V RA4 6 3 — RA5 7 4 AN4 RA6 10 7 — RA7 9 6 — RB0 21 18 AN12 RB1 22 19 AN10 RB2 23 20 AN8 RB3 24 21 ...
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... Development Support............................................................................................................................................................... 217 24.0 Packaging Information.............................................................................................................................................................. 221 Appendix A: Revision History............................................................................................................................................................. 231 Index .................................................................................................................................................................................................. 233 The Microchip Web Site ..................................................................................................................................................................... 237 Customer Change Notification Service .............................................................................................................................................. 237 Customer Support .............................................................................................................................................................................. 237 Reader Response .............................................................................................................................................................................. 238 Product Identification System ............................................................................................................................................................ 239 2011 Microchip Technology Inc. ) ................................................................................................................................ 179 ™ Preliminary PIC16LF1902/3 DS41455B-page 7 ...
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... PIC16LF1902/3 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...
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... DEVICE OVERVIEW The PIC16LF1902/3 are described within this data sheet. They are available in 28-pin packages. Figure 1-1 shows a block diagram PIC16LF1902/3 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device. TABLE 1-1: DEVICE PERIPHERAL ...
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... PIC16LF1902/3 FIGURE 1-1: PIC16LF1902/3 BLOCK DIAGRAM CLKOUT Timing Generation CLKIN INTRC Oscillator MCLR See applicable chapters for more information on peripherals. Note 1: DS41455B-page 10 Program Flash Memory CPU Figure 2-1 Timer0 LCD Timer1 Temp. ADC FVR Indicator 10-Bit Preliminary RAM PORTA PORTB PORTC PORTE ...
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... TABLE 1-2: PIC16LF1902/3 PINOUT DESCRIPTION Name Function RA0/AN0/SEG12 RA0 AN0 SEG12 RA1/AN1/SEG7 RA1 AN1 SEG7 RA2/AN2/COM2 RA2 AN2 COM2 RA3/AN3/V +/COM3/SEG15 RA3 REF AN3 V REF COM3 SEG15 RA4/T0CKI/SEG4 RA4 T0CKI SEG4 RA5/AN4/SEG5 RA5 AN4 SEG5 RA6/CLKOUT/SEG1 RA6 CLKOUT SEG1 RA7/CLKIN/SEG2 RA7 ...
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... PIC16LF1902/3 TABLE 1-2: PIC16LF1902/3 PINOUT DESCRIPTION (CONTINUED) Name Function (1) RB4 /AN11/COM0 RB4 AN11 COM0 (1) RB5 /AN13/COM1 RB5 AN13 COM1 RB6 (1) /ICSPCLK/SEG14 RB6 ICSPCLK SEG14 (1) RB7 /ICSPDAT/SEG13 RB7 ICSPDAT SEG13 RC0/T1OSO/T1CKI RC0 T1OSO T1CKI RC1/T1OSI RC1 T1OSI RC2/SEG3 RC2 SEG3 RC3/SEG6 RC3 ...
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... Section 3.5 “Indirect Addressing” 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 20.0 “Instruction Set Summary” details. 2011 Microchip Technology Inc. Saving”, for more details. for more Preliminary PIC16LF1902/3 DS41455B-page 13 ...
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... PIC16LF1902/3 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration Configuration Configuration Flash Program Memory Program Program Program Bus Bus Bus Instruction Reg Instruction reg Instruction reg 15 15 Instruction Instruction Instruction Decode and Decode & Decode & Control Control Control CLKIN Timing Timing Timing ...
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... The enhanced mid-range core has a 15-bit program counter capable of addressing 32K x 14 program memory space. implemented for the PIC16LF1902/3 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures 3-1, and 3-2) ...
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... PIC16LF1902/3 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16LF1902 PC<14:0> CALL, CALLW 15 RETURN, RETLW Interrupt, RETFIE Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector Interrupt Vector On-chip Program Page 0 Memory Rollover to Page 0 Wraps to Page 0 Wraps to Page 0 Wraps to Page 0 Rollover to Page 0 ...
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... Example 3-2 demonstrates access- ing the program memory via an FSR. The HIGH directive will set bit<7> label points to a location in program memory. 2011 Microchip Technology Inc. PIC16LF1902/3 EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR constants RETLW DATA0 RETLW DATA1 ...
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... PIC16LF1902/3 3.2 Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3): • 12 core registers • 20 Special Function Registers (SFR) • bytes of General Purpose RAM (GPR) • 16 bytes of common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘ ...
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... Note: Digit Borrow out bits, respectively, in subtraction. R-1/q R-1/q R/W-0 Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition (ADDWF, ADDLW, SUBLW, SUBWF instructions) Preliminary PIC16LF1902/3 Section 20.0 Summary”). R/W-0/u R/W-0/u (1) ( bit 0 (1) (1) ...
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... Preliminary BANKED MEMORY PARTITIONING Memory Region 00h Core Registers (12 bytes) 0Bh 0Ch Special Function Registers (20 bytes maximum) 1Fh 20h General Purpose RAM (80 bytes maximum) 6Fh 70h Common RAM (16 bytes) 7Fh maps for PIC16LF1902 and Table 3-3. 2011 Microchip Technology Inc. ...
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... TABLE 3-3: PIC16LF1902/3 MEMORY MAP BANK 0 BANK 1 000h 080h 100h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 00Bh 08Bh 10Bh 00Ch PORTA 08Ch TRISA 10Ch 00Dh PORTB 08Dh TRISB 10Dh 00Eh PORTC 08Eh TRISC 10Eh 00Fh — 08Fh — ...
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... TABLE 3-3: PIC16LF1902/3 MEMORY MAP (CONTINUED) BANK 8 BANK 9 400h 480h 500h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 40Bh 48Bh 50Bh 40Ch 48Ch 50Ch Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ 46Fh 4EFh 56Fh 470h 4F0h ...
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... TABLE 3-3: PIC16LF1902/3 MEMORY MAP (CONTINUED) Bank 15 780h Core Registers (Table 3-2) 78Bh 78Ch Unimplemented Read as ‘0’ 790h LCDCON 791h LCDPS 792h LCDREF 793h LCDCST 794h LCDRL 795h — 796h — 797h LCDSE0 798h LCDSE1 799h — 79Ah LCDSE3 79Bh ...
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... PIC16LF1902/3 3.2.6 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-4 addressed from any Bank. TABLE 3-4: CORE FUNCTION REGISTERS SUMMARY Addr Name Bit 7 Bit 6 Bank 0-31 x00h or Addressing this location uses contents of FSR0H/FSR0L to address data memory INDF0 x80h ...
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... Legend: Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Note 1: Unimplemented, read as ‘1’. 2: 2011 Microchip Technology Inc. PIC16LF1902/3 Bit 5 Bit 4 Bit 3 Bit 2 — — RE3 — ...
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... PIC16LF1902/3 TABLE 3-5: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Addr Name Bit 7 Bit 6 Bank 2 10Ch LATA PORTA Data Latch 10Dh LATB PORTB Data Latch 10Eh LATC PORTC Data Latch 10Fh to — Unimplemented 115h 116h BORCON SBOREN BORFS 117h FVRCON FVREN FVRRDY 118h to — ...
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... Legend: Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Note 1: Unimplemented, read as ‘1’. 2: 2011 Microchip Technology Inc. PIC16LF1902/3 Bit 5 Bit 4 Bit 3 Bit 2 IOCBP5 IOCBP4 IOCBP3 IOCBP2 ...
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... PIC16LF1902/3 TABLE 3-5: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Addr Name Bit 7 Bit 6 Bank 15 (Continued) 7ABh — Unimplemented 7ACh LCDDATA12 — — 7ADh — Unimplemented 7AEh — Unimplemented 7AFh LCDDATA15 — — 7B0h — Unimplemented 7B1h — Unimplemented 7B2h LCDDATA18 — — ...
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... If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will 0 be loaded with the address BRW If using BRA, the entire PC will be loaded with the signed value of the operand of the BRA instruction. 0 BRA Preliminary PIC16LF1902/3 DS41455B-page 29 ...
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... PIC16LF1902/3 3.4 Stack All devices have a 16-level x 15-bit wide hardware stack (refer to Figures 3-3 and 3-3). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instruc- tions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution ...
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... FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 TOSH:TOSL FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3 TOSH:TOSL 2011 Microchip Technology Inc. PIC16LF1902/3 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. 0x08 ...
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... PIC16LF1902/3 FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.4.2 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Word 2 is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register ...
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... FIGURE 3-9: INDIRECT ADDRESSING FSR Address Range Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: 2011 Microchip Technology Inc. PIC16LF1902/3 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory ...
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... PIC16LF1902/3 3.5.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR ...
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... Location Select 0x2000 0x29AF 2011 Microchip Technology Inc. PIC16LF1902/3 3.5.3 PROGRAM FLASH MEMORY To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF ...
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... PIC16LF1902/3 NOTES: DS41455B-page 36 Preliminary 2011 Microchip Technology Inc. ...
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... Configuration Word 2 at 8008h. The DEBUG bit in Configuration Word 2 is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’. 2011 Microchip Technology Inc. PIC16LF1902/3 by device Preliminary DS41455B-page 37 ...
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... PIC16LF1902/3 REGISTER 4-1: CONFIGURATION WORD 1 U-1 — bit 13 R/P-1 R/P-1 R/P-1 CP MCLRE PWRTE bit 7 Legend Readable bit P = Programmable bit ‘0’ = Bit is cleared ‘1’ = Bit is set bit 13-12 Unimplemented: Read as ‘1’ bit 11 CLKOUTEN: Clock Out Enable bit 1 = CLKOUT function is disabled. I/O function on the CLKOUT pin. ...
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... Unimplemented: Read as ‘1’ bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits 2 kW Flash memory (PIC16LF1902 only Write protection off 10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified by PMCON control 01 = 000h to 3FFh write-protected, 400h to 7FFh may be modified by PMCON control 00 = 000h to 7FFh write-protected, no addresses may be modified by PMCON control ...
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... PIC16LF1902/3 4.2 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection is controlled independently. Internal access to the program memory is unaffected by any code protection setting. 4.2.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Word 1 ...
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... These bits are used to identify the revision (see Table under DEV<8:0> above). 2011 Microchip Technology Inc DEV<8:3> REV<4:0> Unimplemented bit, read as ‘1’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit DEVICEID<13:0> Values DEV<8:0> REV<4:0> x xxxx x xxxx Preliminary PIC16LF1902 bit bit 0 DS41455B-page 41 ...
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... PIC16LF1902/3 NOTES: DS41455B-page 42 Preliminary 2011 Microchip Technology Inc. ...
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... External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset LPBOR Reset BOR Enable 2011 Microchip Technology Inc. PIC16LF1902/3 A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1. PWRT Zero 64 ms LFINTOSC PWRTEN Preliminary Device Reset DS41455B-page 43 ...
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... PIC16LF1902/3 5.1 Power-on Reset (POR) The POR circuit holds the device in Reset until V reached an acceptable level for minimum operation. Slow rising V , fast operating speeds or analog DD performance may require greater than minimum V The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met ...
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... Band gap operates normally, and may turn off bit 5-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive 2011 Microchip Technology Inc. PIC16LF1902/3 (1) T PWRT < T PWRT PWRT (1) T ...
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... PIC16LF1902/3 5.3 Low-Power Brown-out Reset (LPBOR) The Low-Power Brown-Out Reset (LPBOR essential part of the Reset subsystem. Refer to Figure 5-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external V When too low of a voltage is detected, the device is held in Reset ...
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... FIGURE 5-3: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2011 Microchip Technology Inc. PIC16LF1902/3 T PWRT T MCLR T OST Preliminary DS41455B-page 47 ...
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... PIC16LF1902/3 5.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 5-3 and Table 5-4 show the Reset condi- tions of these registers. TABLE 5-3: RESET STATUS BITS AND THEIR SIGNIFICANCE ...
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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2011 Microchip Technology Inc. PIC16LF1902/3 The PCON register bits are shown in R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q RWDT RMCLR Bit is set by hardware U = Unimplemented bit, read as ‘ ...
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... PIC16LF1902/3 TABLE 5-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 BORCON SBOREN BORFS PCON STKOVF STKUNF STATUS — — WDTCON — — Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets. DS41455B-page 50 Bit 5 Bit 4 Bit 3 Bit 2 — ...
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... The INTOSC internal oscillator block produces a low and high frequency clock source, LFINTOSC and HFINTOSC. (see Internal Oscillator Block, Figure 6-1). A wide selection of device clock frequencies may be derived from these two clock sources. 2011 Microchip Technology Inc. PIC16LF1902/3 Figure 6-1 designated Preliminary DS41455B-page 51 ...
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... PIC16LF1902/3 FIGURE 6-1: SIMPLIFIED PIC CLKIN EC CLKIN Secondary Oscillator T1CKI/ Secondary T1OSO Oscillator (T1OSC) T1OSI Internal Oscillator IRCF<3:0> Start-up Control Logic 16 MHz Primary Osc Start-Up Osc LF-INTOSC (31 kHz) DS41455B-page 52 ® MCU CLOCK SOURCE BLOCK DIAGRAM Secondary Clock 4 4 HF-16 MHz /1 1111 ...
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... High power, 4-20 MHz (FOSC = 11) • Medium power, 0.5-4 MHz (FOSC = 10) • Low power, 0-0.5 MHz (FOSC = 01) 2011 Microchip Technology Inc. PIC16LF1902/3 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...
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... PIC16LF1902/3 6.2.1.2 Secondary Oscillator The secondary oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral opti- mized for timekeeping operations with a 32.768 kHz crystal connected between the T1CKI/T1OSO and T1OSI device pins. The secondary oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching ...
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... Microchip Technology Inc. PIC16LF1902/3 Following any Reset, the IRCF<3:0> bits Note: of the OSCCON register are set to ‘0111’ and the frequency selection is set to 500 kHz. The user can modify the IRCF bits to select a different frequency. The IRCF< ...
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... PIC16LF1902/3 FIGURE 6-4: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC LFINTOSC (WDT disabled) HFINTOSC LFINTOSC 0 IRCF <3:0> System Clock HFINTOSC LFINTOSC (WDT enabled) HFINTOSC LFINTOSC IRCF <3:0> System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time HFINTOSC IRCF <3:0> System Clock ...
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... FOSC<1:0> bits in the Configuration Word 1, or from the internal clock source. The OST does not reflect the status of the secondary oscillator. 2011 Microchip Technology Inc. PIC16LF1902/3 6.3.3 SECONDARY OSCILLATOR The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral optimized for timekeeping operations with a 32 ...
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... PIC16LF1902/3 6.4 Oscillator Control Registers REGISTER 6-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R/W-0/0 R/W-1/1 — bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits 000x = 31 kHz LF 001x = 31 ...
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... IRCF<3:0> — OSTS HFIOFR — — T1CKPS<1:0> T1OSCEN T1SYNC Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 — — CLKOUTEN PWRTE WDTE<1:0> Preliminary PIC16LF1902/3 U-0 R-0/0 R-0/q LFIOFR HFIOFS — bit 0 Register Bit 1 Bit 0 on Page SCS<1:0> 58 LFIOFR HFIOFS 59 — TMR1ON ...
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... PIC16LF1902/3 NOTES: DS41455B-page 60 Preliminary 2011 Microchip Technology Inc. ...
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... Many peripherals produce Interrupts. Refer to the cor- responding chapters for details. FIGURE 7-1: INTERRUPT LOGIC Peripheral Interrupts (TMR1IF) PIR1<0> (TMR1IF) PIR1<0> PIRn<7> PIEn<7> 2011 Microchip Technology Inc. PIC16LF1902/3 A block diagram of the interrupt logic is shown in Figure 7.1 and Figure 7.1. TMR0IF TMR0IE INTF INTE ...
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... PIC16LF1902/3 7.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt Enable bit(s) for the specific interrupt event(s) • PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the ...
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... Q1 PC+1 0004h Inst(PC) NOP NOP PC+1/FSR New PC/ 0004h ADDR PC+1 Inst(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP Preliminary PIC16LF1902/3 0005h Inst(0004h) 0005h Inst(0004h) 0004h 0005h Inst(0004h) Inst(0005h) NOP 0004h 0005h Inst(0004h) NOP NOP DS41455B-page 63 ...
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... PIC16LF1902/3 FIGURE 7-3: INT PIN INTERRUPT TIMING CLKIN (3) CLKOUT (4) INT pin (1) INTF (5) GIE INSTRUCTION FLOW PC PC Instruction Inst (PC) Fetched Instruction Inst (PC – 1) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 T Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. ...
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... ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved. 2011 Microchip Technology Inc. PIC16LF1902/3 Section 8.0 Preliminary DS41455B-page 65 ...
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... PIC16LF1902/3 7.6 Interrupt Control Registers 7.6.1 INTCON REGISTER The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, interrupt-on-change and external INT pin interrupts. REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 ...
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... Unimplemented: Read as ‘0’ bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt 2011 Microchip Technology Inc. PIC16LF1902/3 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. U-0 U-0 U-0 — ...
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... PIC16LF1902/3 7.6.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as shown in Register 7-3. REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘ ...
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... TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending 2011 Microchip Technology Inc. PIC16LF1902/3 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. ...
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... PIC16LF1902/3 7.6.5 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as shown in Register 7-5. REGISTER 7-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘ ...
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... TMR0IE INTE IOCIE TMR0IF PSA — — — — — — — LCDIE — — — — — — — LCDIF Preliminary PIC16LF1902/3 Register Bit 1 Bit 0 on Page INTF IOCIF 66 PS<2:0> 131 — TMR1IE 67 — — 68 — TMR1IF 69 — — 70 DS41455B-page 71 ...
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... PIC16LF1902/3 NOTES: DS41455B-page 72 Preliminary 2011 Microchip Technology Inc. ...
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... Examples of internal circuitry that might be sourcing current include the FVR module. See 13.0 “Fixed Volt- for more information. age Reference (FVR)” 2011 Microchip Technology Inc. PIC16LF1902/3 8.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. ...
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... PIC16LF1902/3 8.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP ...
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... Configurable time-out period is from 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2011 Microchip Technology Inc. PIC16LF1902/3 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41455B-page 75 ...
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... PIC16LF1902/3 9.1 Independent Clock Source The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Section 21.0 “Electrical Specifications” LFINTOSC tolerances. 9.2 WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE< ...
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... R/W-1/1 WDTPS<4:0> Unimplemented bit, read as ‘0’ -m/n = Value at POR and BOR/Value at all other Resets ( (Interval 4s nominal (Interval 8s nominal (Interval 16s nominal (Interval 32s nominal (Interval 64s nominal (Interval 128s nominal (Interval 256s nominal) Preliminary PIC16LF1902/3 R/W-1/1 R/W-0/0 SWDTEN bit 0 DS41455B-page 77 ...
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... PIC16LF1902/3 TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Name Bit 7 Bit 6 OSCCON — STATUS — — WDTCON — — unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer. Legend: TABLE 9-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER ...
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... In this case not necessary to save and rewrite the other previously programmed locations. See Table 10-1 write latches for Flash program memory. Preliminary PIC16LF1902/3 for Erase Row size and the number of DS41455B-page 79 ...
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... PIC16LF1902/3 TABLE 10-1: FLASH MEMORY ORGANIZATION BY DEVICE Row Erase Device (words) PIC16(L)F1526 32 PIC16(L)F1527 10.2.1 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must: 1. Write the desired address PMADRH:PMADRL register pair. 2. Clear the CFGS bit of the PMCON1 register. 3. Then, set control bit RD of the PMCON1 register. ...
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... MOVF PMDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2011 Microchip Technology Inc. PIC16LF1902/3 PMADRH,PMADRL PC+3 INSTR ( PMDATH,PMDATL INSTR ( INSTR( INSTR( instruction ignored instruction ignored Forced NOP Forced NOP ...
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... PIC16LF1902/3 10.2.2 FLASH MEMORY UNLOCK SEQUENCE The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write pro- gramming or erasing. The sequence must be executed and completed without interruption to successfully complete any of the following operations: • Row Erase • Load program memory write latches • ...
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... This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the PMCON1 WRITE instruc- tion. 2011 Microchip Technology Inc. PIC16LF1902/3 FIGURE 10-4: FLASH PROGRAM MEMORY ERASE FLOWCHART Erase Operation ...
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... PIC16LF1902/3 EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY ; This row erase routine assumes the following valid address within the erase row is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF INTCON,GIE BANKSEL PMADRL MOVF ADDRL,W ...
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... Microchip Technology Inc. PIC16LF1902/3 The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts. First, each write latch is loaded with data from the PMDATH:PMDATL using the unlock sequence with LWLO = 1 ...
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FIGURE 10-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES PMADRH - Row PMADRH<6:0> Address :PMADRL<7:5> Decode ...
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... Program or Config. Memory (CFGS) Select Row Address (PMADRH:PMADRL) Select Write Operation (FREE = 0) Load Write Latches Only (LWLO = 1) 2011 Microchip Technology Inc. PIC16LF1902/3 Enable Write/Erase Operation (WREN = 1) Load the value to write (PMDATH:PMDATL) Update the word counter (word_cnt--) Yes Last word to write ? ...
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... PIC16LF1902/3 EXAMPLE 10-3: WRITING TO FLASH PROGRAM MEMORY ; This write routine assumes the following bytes of data are loaded, starting at the address in DATA_ADDR ; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, ; stored in little endian format ; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL ...
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... Erase the program memory row. 6. Load the write latches with data from the RAM image. 7. Initiate a programming operation. 2011 Microchip Technology Inc. PIC16LF1902/3 FIGURE 10-7: FLASH PROGRAM MEMORY MODIFY FLOWCHART Start Modify Operation Read Operation (Figure x.x) Figure 10-2 ...
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... PIC16LF1902/3 10.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the user ID’s, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<15> but not all addresses are accessible. ...
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... RAM. This image will be used to verify the data currently stored in Flash Program Memory. Read Operation (Figure x.x) Figure 10-2 PMDAT = No RAM image ? Fail Yes Verify Operation No Last Word ? Yes End Verify Operation 2011 Microchip Technology Inc. PIC16LF1902/3 Preliminary DS41455B-page 91 ...
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... PIC16LF1902/3 10.6 Flash Program Memory Control Registers REGISTER 10-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER R/W-x/u R/W-x/u R/W-x/u bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PMDAT<7:0>: Read/write value for Least Significant bits of program memory ...
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... Unimplemented bit, read as ‘ 1 ’. Note 1: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started ( The LWLO bit is ignored during a program memory erase operation (FREE = 2011 Microchip Technology Inc. PIC16LF1902/3 (2) R/W/HC-0/0 R/W/HC-x/q R/W-0/0 FREE WRERR WREN U = Unimplemented bit, read as ‘ ...
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... PIC16LF1902/3 REGISTER 10-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 bit 7 Legend Readable bit W = Writable bit S = Bit can only be set x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the PMCON1 register ...
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... A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in 2011 Microchip Technology Inc. PIC16LF1902/3 FIGURE 11-1: Write LATx Write PORTx Data Register ...
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... PIC16LF1902/3 11.1 PORTA Registers PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 11-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin) ...
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... Bit is cleared bit 7-4 LATA<7:0>: PORTA Output Latch Value bits Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of Note 1: actual I/O pin values. 2011 Microchip Technology Inc. PIC16LF1902/3 R/W-x/x R-x/x R/W-x/x RA4 RA3 RA2 U = Unimplemented bit, read as ‘ ...
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... PIC16LF1902/3 REGISTER 11-4: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 — — ANSA5 bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 ANSA5: Analog Select between Analog or Digital Function on pins RA5, respectively 0 = Digital I/O ...
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... TABLE 11-5: Pin Name RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 Priority listed from highest to lowest. Note 1: Preliminary PIC16LF1902/3 11-5. Table 11-5. PORTB OUTPUT PRIORITY (1) Function Priority SEG0 AN12 INT IOC RB0 SEG24 AN10 VLCD1 ...
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... PIC16LF1902/3 REGISTER 11-5: PORTB: PORTB REGISTER R/W-x/u R/W-x/u R/W-x/u RB7 RB6 RB5 bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 RB<7:0>: PORTB General Purpose I/O Pin bits 1 = Port pin is > Port pin is < ...
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... TRISB7 TRISB6 WPUB WPUB7 WPUB6 x = unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTB. Legend: 2011 Microchip Technology Inc. PIC16LF1902/3 R/W-1/1 R/W-1/1 R/W-1/1 ANSB4 ANSB3 ANSB2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) ...
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... PIC16LF1902/3 11.3 PORTC Registers PORTC is an 8-bit wide bidirectional port. The corresponding data direction register (Register 11-6). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i ...
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... Bit is cleared bit 7-0 LATC<7:0>: PORTC Output Latch Value bits Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is Note 1: return of actual I/O pin values. 2011 Microchip Technology Inc. PIC16LF1902/3 R/W-x/u R/W-x/u R/W-x/u RC4 RC3 RC2 U = Unimplemented bit, read as ‘ ...
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... PIC16LF1902/3 TABLE 11-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 LATC LATC7 LATC6 PORTC RC7 RC6 TRISC TRISC7 TRISC6 x = unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. Legend: DS41455B-page 104 Bit 5 Bit 4 Bit 3 Bit 2 LATC5 ...
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... Unimplemented: Read as ‘0’ bit 3 Unimplemented: Read as ‘1’ bit 2-0 Unimplemented: Read as ‘0’ Unimplemented, read as ‘1’. Note 1: 2011 Microchip Technology Inc. PIC16LF1902/3 11.4.1 PORTE FUNCTIONS AND OUTPUT PRIORITIES No output priorities, RE3 is an input only pin. U-0 R-x/u U-0 RE3 — ...
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... PIC16LF1902/3 REGISTER 11-15: WPUE: WEAK PULL-UP PORTE REGISTER U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 WPUE: Weak Pull-up Register bit ...
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... RBx IOCBPx 2011 Microchip Technology Inc. PIC16LF1902/3 12.3 Interrupt Flags The IOCBFx bits located in the IOCBF register are status flags that correspond to the Interrupt-on-change pins of PORTB expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set ...
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... PIC16LF1902/3 REGISTER 12-1: IOCBP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 IOCBP7 IOCBP6 IOCBP5 bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 IOCBP<7:0>: Interrupt-on-Change Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will be set upon detecting an edge ...
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... INTE IOCIE TMR0IF IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBP5 IOCBP4 IOCBP3 IOCBP2 TRISB5 TRISB4 TRISB3 TRISB2 Preliminary PIC16LF1902/3 Register Bit 1 Bit 0 on Page ANSB1 ANSB0 101 INTF IOCIF 66 IOCBF1 IOCBF0 108 IOCBN1 IOCBN0 108 IOCBP1 IOCBP0 108 TRISB1 ...
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... PIC16LF1902/3 NOTES: DS41455B-page 110 Preliminary 2011 Microchip Technology Inc. ...
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... FVRRDY - INTOSC is active and device is not in Sleep BOR always enabled BOR disabled in Sleep mode, BOR Fast Start enabled. BOR under software control, BOR Fast Start enabled Preliminary PIC16LF1902/3 independent programmable gain for additional information. for the FVR BUFFER1 (To ADC Module) Description ...
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... PIC16LF1902/3 13.3 FVR Control Registers REGISTER 13-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 (1) FVREN FVRRDY TSEN bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 FVREN: Fixed Voltage Reference Enable bit ...
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... ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200 s between sequential conversions of the temperature indicator output. Preliminary PIC16LF1902/3 TEMPERATURE CIRCUIT DIAGRAM V DD TSEN ...
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... PIC16LF1902/3 NOTES: DS41455B-page 114 Preliminary 2011 Microchip Technology Inc. ...
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... ADC 01000 01001 GO/DONE 01010 01011 01100 (1) ADON 01101 V SS 11101 11110 11111 (2) (Example 15-1) for detailed analog channel selection per device. Preliminary PIC16LF1902 Left Justify ADFM 1 = Right Justify 16 ADRESH ADRESL DS41455B-page 115 ...
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... PIC16LF1902/3 15.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • Port configuration • Channel selection • ADC voltage reference selection • ADC conversion clock source • Interrupt control • Result formatting 15.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals ...
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... the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. Preliminary PIC16LF1902/3 ) OSC 4 MHz 1 MHz 2.0 s (2) 500 ns (2) (2) 1.0 s 4.0 s 2.0 s 8.0 s (3) 4.0 s 16.0 s (3) 8.0 s (3) 32.0 ...
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... PIC16LF1902/3 15.1.5 INTERRUPTS The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software ...
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... Note: Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2011 Microchip Technology Inc. PIC16LF1902/3 15.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...
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... PIC16LF1902/3 15.2.5 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. Configure Port: • Disable pin output driver (Refer to the TRIS register) • Configure pin as analog (Refer to the ANSEL register) 2. Configure the ADC module: • Select ADC conversion clock • ...
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... ADC is disabled and consumes no operating current See Note 1: Section 13.0 “Fixed Voltage Reference (FVR)” See 2: Section 14.0 “Temperature Indicator Module” 2011 Microchip Technology Inc. PIC16LF1902/3 R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (2) (1) for more information ...
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... PIC16LF1902/3 REGISTER 15-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 ADFM ADCS<2:0> bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is loaded Left justified. Six Least Significant bits of ADRESL are set to ‘ ...
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... Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. 2011 Microchip Technology Inc. PIC16LF1902/3 R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
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... PIC16LF1902/3 REGISTER 15-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u — — — bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES< ...
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... HOLD Preliminary PIC16LF1902/3 Equation 15-1 may be 5. Temperature Coefficient charged to within 1/2 lsb CHOLD charge response to V CHOLD APPLIED ...
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... PIC16LF1902/3 FIGURE 15-4: ANALOG INPUT MODEL Analog Input pin Rs C PIN Sample/Hold Capacitance Legend: HOLD C = Input Capacitance PIN I = Leakage current at the pin due to LEAKAGE various junctions R = Interconnect Resistance Resistance of Sampling Switch Sampling Switch V = Threshold Voltage T Refer to Note 1: Section 21.0 “Electrical Specifications” ...
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... TRISA5 TRISA4 TRISA3 TRISA2 TRISB5 TRISB4 TRISB3 TRISB2 TSEN TSRNG — — Preliminary PIC16LF1902/3 Register Bit 1 Bit 0 on Page 121 GO/DONE ADON ADPREF1 ADPREF0 122 123, 124 123, 124 ANSA1 ANSA0 98 ANSB1 ANSB0 101 ...
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... PIC16LF1902/3 NOTES: DS41455B-page 128 Preliminary 2011 Microchip Technology Inc. ...
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... T0CKI 1 TMR0SE TMR0CS 2011 Microchip Technology Inc. PIC16LF1902/3 16.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘ ...
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... PIC16LF1902/3 16.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. The Watchdog Timer (WDT) uses its own Note: independent prescaler. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS< ...
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... Value at POR and BOR/Value at all other Resets /4) OSC 128 1 : 256 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF PSA TRISA5 TRISA4 TRISA3 TRISA2 Preliminary PIC16LF1902/3 R/W-1/1 R/W-1/1 PS<2:0> bit 0 Register Bit 1 Bit 0 on Page INTF IOCIF 66 PS<2:0> 131 129* TRISA1 TRISA0 97 DS41455B-page 131 ...
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... PIC16LF1902/3 NOTES: DS41455B-page 132 Preliminary 2011 Microchip Technology Inc. ...
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... R TMR1ON (2) EN T1CLK TMR1L Q D TMR1CS<1:0> T1SYNC Reserved 11 Prescaler T1CKPS<1:0> F OSC Internal 01 Clock F /4 OSC Internal 00 Clock Preliminary PIC16LF1902/3 0 Data Bus T1GVAL T1GCON EN Q1 Interrupt Set TMR1GIF det TMR1GE Synchronized 0 clock input 1 (3) Synchronize det OSC Sleep input Internal Clock To LCD and Clock Switching Modules ...
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... PIC16LF1902/3 17.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and incre- ments on every selected edge of the external source ...
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... Polarity selection is controlled by the T1GPOL bit of the T1GCON register. TABLE 17-4: T1GSS Timer1 Gate Pin 00 Overflow of Timer0 01 (TMR0 increments from FFh to 00h) Preliminary PIC16LF1902/3 Figure 17-3 for timing details. TIMER1 GATE ENABLE SELECTIONS T1G Timer1 Operation Counts 0 0 Holds Count ...
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... PIC16LF1902/3 17.6.2.1 T1G Pin Gate Operation The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. 17.6.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry ...
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... Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2011 Microchip Technology Inc. PIC16LF1902/3 17.8 Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode ...
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... PIC16LF1902/3 FIGURE 17-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 17-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 DS41455B-page 138 Preliminary 2011 Microchip Technology Inc ...
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... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF 2011 Microchip Technology Inc. PIC16LF1902/3 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary Cleared by software DS41455B-page 139 ...
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... PIC16LF1902/3 FIGURE 17-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41455B-page 140 Set by hardware on falling edge of T1GVAL Preliminary 2011 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 gate flip-flop 2011 Microchip Technology Inc. PIC16LF1902/3 R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
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... PIC16LF1902/3 17.10 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), shown in Register 17-2, is used to control Timer1 gate. REGISTER 17-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u TMR1GE T1GPOL T1GTM bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘ ...
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... INTE IOCIE TMR0IF — — — — — — TRISC5 TRISC4 TRISC3 TRISC2 T1CKPS<1:0> T1OSCEN T1SYNC T1GTM T1GSPM T1GGO/ T1GVAL DONE Preliminary PIC16LF1902/3 Register Bit 1 Bit 0 on Page INTF IOCIF 66 — — TMR1IE 67 — — TMR1IF 69 137* 137* TRISC1 TRISC0 103 — ...
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... PIC16LF1902/3 NOTES: DS41455B-page 144 Preliminary 2011 Microchip Technology Inc. ...
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... DRIVER MODULE The Liquid Crystal Display (LCD) Driver module generates the timing control to drive a static or multiplexed LCD panel. In the PIC16LF1902/3 device, the module drives the panels four commons and total segments. The LCD module also provides control of the LCD pixel data. ...
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... PIC16LF1902/3 TABLE 18-1: LCD SEGMENT AND DATA REGISTERS # of LCD Registers Device Segment Enable PIC16LF1902/3 3 The LCDCON register (Register 18-1) controls the operation of the LCD Driver module. The LCDPS reg- ister (Register 18-2) configures the LCD clock source prescaler and the type of waveform; Type-A or Type-B. ...
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... On these devices, COM3 and SEG15 are shared on one pin, limiting the device from driving 72 segments. Note 1: 2011 Microchip Technology Inc. PIC16LF1902/3 U-0 R/W-0/0 R/W-0/0 CS<1:0> — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets C = Only clearable bit Maximum Number of Pixels PIC16LF1902 (1) 72 Preliminary R/W-1/1 R/W-1/1 LMUX<1:0> bit 0 Bias Static ...
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... PIC16LF1902/3 REGISTER 18-2: LCDPS: LCD PHASE REGISTER R/W-0/0 R/W-0/0 R-0/0 WFT BIASMD LCDA bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WFT: Waveform Type bit 1 = Type-B phase changes on each frame boundary ...
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... The VLCD1 pin is connected to the internal bias voltage LCDBIAS1 0 = The VLCD1 pin is not connected bit 0 Unimplemented: Read as ‘0’ Normal pin controls of TRISx and ANSELx are unaffected. Note 1: 2011 Microchip Technology Inc. PIC16LF1902/3 U-0 R/W-0/0 R/W-0/0 — VLCD3PE VLCD2PE U = Unimplemented bit, read as ‘0’ ...
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... PIC16LF1902/3 REGISTER 18-4: LCDCST: LCD CONTRAST CONTROL REGISTER U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 LCDCST<2:0>: LCD Contrast Control bits ...
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... Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SEGx-COMy: Pixel On bits 1 = Pixel on (dark Pixel off (clear) 2011 Microchip Technology Inc. PIC16LF1902/3 R/W-0/0 R/W-0/0 R/W-0/0 SEn SEn SEn U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
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... PIC16LF1902/3 18.2 LCD Clock Source Selection The LCD module has 3 possible clock sources: • F /256 OSC • T1OSC • LFINTOSC The first clock source is the system clock divided by 256 (F /256). This divider ratio is chosen to provide OSC about 1 kHz output when the system clock is 8 MHz. ...
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... So that the user is not forced to place external compo- nents and use up to three pins for bias voltage generation, internal contrast control and an internal reference ladder are provided internally to the PIC16LF1902/3. Both of these features may be used in conjunction with the exter- nal VLCD<3:1> pins, to provide maximum flexibility. Refer ...
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... PIC16LF1902/3 18.4 LCD Bias Internal Reference Ladder The internal reference ladder can be used to divide the LCD bias voltage two or three equally spaced voltages that will be supplied to the LCD segment pins. To create this, the reference ladder consists of three matched resistors. Refer to Figure 18-3 ...
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... COM0 SEG0 COM0-SEG0 2011 Microchip Technology Inc. PIC16LF1902/3 The LCDRL register allows switching between two power modes, designated ‘A’ and ‘B’. ‘A’ Power mode is active for a programmable time, beginning at the time when the LCD segments transition. ‘B’ Power mode is the remaining time before the segments or commons change again. The LRLAT< ...
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FIGURE 18-5: LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE A WAVEFORM (1/2 MUX, 1/2 BIAS DRIVE) Single Segment Time 32 kHz Clock Ladder Power ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 Control Segment Clock Segment Data ...
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FIGURE 18-6: LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE B WAVEFORM (1/2 MUX, 1/2 BIAS DRIVE) Single Segment Time 32 kHz Clock Ladder Power ‘H00 ‘H01 ‘H02 ‘H03 ‘H0E ‘H0F Control Segment Clock Segment Data Power Mode ...
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... PIC16LF1902/3 REGISTER 18-7: LCDRL: LCD REFERENCE LADDER CONTROL REGISTERS R/W-0/0 R/W-0/0 R/W-0/0 LRLAP<1:0> LRLBP<1:0> bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 LRLAP<1:0>: LCD Reference Ladder A Time Power Control bits ...
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... The LCD module automatically turns on the Note: Fixed Voltage Reference when needed. 2011 Microchip Technology Inc. PIC16LF1902/3 The contrast control circuit is used to decrease the output voltage of the signal source by a total of approximately 10%, when LCDCST = 111. Whenever the LCD module is inactive (LCDA = 0), the contrast control ladder will be turned off (open) ...
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... PIC16LF1902/3 18.5 LCD Multiplex Types The LCD Driver module can be configured into one of four multiplex types: • Static (only COM0 is used) • 1/2 multiplex (COM<1:0> are used) • 1/3 multiplex (COM<2:0> are used) • 1/4 multiplex (COM<3:0> are used) The LMUX<1:0> bit setting of the LCDCON register ...
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... LCDDATA7, 1 LCDDATA4, 2 LCDDATA7, 2 LCDDATA4, 3 LCDDATA7, 3 LCDDATA4, 4 LCDDATA7, 4 LCDDATA4, 5 LCDDATA7, 5 LCDDATA4, 6 LCDDATA7, 6 LCDDATA4, 7 LCDDATA7, 7 LCDDATA5, 5 LCDDATA8, 5 LCDDATA5, 6 LCDDATA8, 6 LCDDATA5, 7 LCDDATA8, 7 Preliminary PIC16LF1902/3 COM3 LCD LCDDATAx LCD Segment Address Segment LCDDATA9, 0 LCDDATA9, 1 LCDDATA9, 2 LCDDATA9, 3 LCDDATA9, 4 LCDDATA9, 5 LCDDATA9, 6 LCDDATA9, 7 LCDDATA10, 0 LCDDATA10, 1 LCDDATA10, 2 LCDDATA10, 3 LCDDATA10, 4 ...
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... PIC16LF1902/3 18.9 LCD Waveform Generation LCD waveforms are generated so that the net AC voltage across the dark pixel should be maximized and the net AC voltage across the clear pixel should be minimized. The net DC voltage across any pixel should be zero. The COM signal represents the time slice for each common, while the SEG contains the pixel data ...
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... FIGURE 18-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM0 pin COM1 COM1 pin COM0 SEG0 pin SEG1 pin COM0-SEG0 segment voltage COM0-SEG1 segment voltage (inactive) 1 Frame = 2 single segment times. Note: 2011 Microchip Technology Inc. (active) 1 Frame 1 Segment Time Preliminary PIC16LF1902 ...
Page 164
... PIC16LF1902/3 FIGURE 18-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM1 COM0 pin COM0 COM1 pin SEG0 pin SEG1 pin COM0-SEG0 segment voltage COM0-SEG1 segment voltage (inactive) 1 Frame = 2 single segment times. Note: DS41455B-page 164 (active) 2 Frames 1 Segment Time Preliminary 2011 Microchip Technology Inc. ...
Page 165
... FIGURE 18-11: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 pin COM0 COM1 pin SEG0 pin SEG1 pin COM0-SEG0 segment voltage COM0-SEG1 segment voltage (inactive) 1 Frame = 2 single segment times. Note: 2011 Microchip Technology Inc. (active) 1 Frame 1 Segment Time Preliminary PIC16LF1902 ...
Page 166
... PIC16LF1902/3 FIGURE 18-12: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 pin COM0 COM1 pin SEG0 pin SEG1 pin COM0-SEG0 segment voltage COM0-SEG1 segment voltage (inactive) 1 Frame = 2 single segment times. Note: DS41455B-page 166 (active) 2 Frames 1 Segment Time Preliminary 2011 Microchip Technology Inc. ...
Page 167
... TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 segment voltage COM0-SEG1 segment voltage 1 Frame = 2 single segment times. Note: 2011 Microchip Technology Inc. COM0 pin COM1 pin COM2 pin SEG0 and SEG2 pins SEG1 pin (inactive) (active) 1 Segment Time Preliminary PIC16LF1902 ...
Page 168
... PIC16LF1902/3 FIGURE 18-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 segment voltage COM0-SEG1 segment voltage 1 Frame = 2 single segment times. Note: DS41455B-page 168 COM0 pin COM1 pin COM2 pin SEG0 pin SEG1 pin (inactive) (active) 1 Segment Time Preliminary ...
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... TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 segment voltage COM0-SEG1 segment voltage 1 Frame = 2 single segment times. Note: 2011 Microchip Technology Inc. COM0 pin COM1 pin COM2 pin SEG0 and SEG2 pins SEG1 pin (inactive) (active) 1 Segment Time Preliminary PIC16LF1902 ...
Page 170
... PIC16LF1902/3 FIGURE 18-16: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 segment voltage COM0-SEG1 segment voltage 1 Frame = 2 single segment times. Note: DS41455B-page 170 COM0 pin COM1 pin COM2 pin SEG0 pin SEG1 pin (inactive) (active) 1 Segment Time Preliminary ...
Page 171
... TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM0 pin COM2 COM1 pin COM1 COM0 COM2 pin COM3 pin COM0-SEG0 segment voltage COM0-SEG1 segment voltage 1 Frame = 2 single segment times. Note: 2011 Microchip Technology Inc. SEG0 pin SEG1 pin (active) (inactive) 1 Frame 1 Segment Time Preliminary PIC16LF1902 ...
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... PIC16LF1902/3 FIGURE 18-18: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM0 pin COM2 COM1 pin COM1 COM0 COM2 pin COM3 pin COM0-SEG0 segment voltage COM0-SEG1 segment voltage 1 Frame = 2 single segment times. Note: DS41455B-page 172 SEG0 pin SEG1 pin (active) (inactive) ...
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... WERR bit of the LCDCON register is set and the write does not occur. The LCD frame interrupt is not generated Note: when the Type-A waveform is selected and when the Type-B with no multiplex (static) is selected. 2011 Microchip Technology Inc. PIC16LF1902 FINT Preliminary DS41455B-page 173 ...
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... PIC16LF1902/3 FIGURE 18-19: WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE (EXAMPLE – TYPE-B, NON-STATIC) COM0 COM1 COM2 COM3 Frame Boundary /2*(LMUX<1:0> FWR FRAME + 40 ns)) minimum = 1.5 – FINT FWR ns)) maximum = 1.5 – FWR CY DS41455B-page 174 LCD Interrupt Occurs 2 Frames ...
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... CPU and other peripherals. 2011 Microchip Technology Inc. PIC16LF1902/3 Table 18-8 shows the status of the LCD module during a Sleep while using each of the three available clock sources ...
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... PIC16LF1902/3 FIGURE 18-20: SLEEP ENTRY/EXIT WHEN SLPEN = 1 COM0 COM1 COM2 SEG0 2 Frames SLEEP Instruction Execution DS41455B-page 176 Wake-up Preliminary 2011 Microchip Technology Inc ...
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... Disabling the LCD Module To disable the LCD module, write all ‘0’s to the LCDCON register. 2011 Microchip Technology Inc. PIC16LF1902/3 18.14 LCD Current Consumption When using the LCD module the current consumption consists of the following three factors: • Oscillator Selection • ...
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... PIC16LF1902/3 TABLE 18-9: SUMMARY OF REGISTERS ASSOCIATED WITH LCD OPERATION Name Bit 7 Bit 6 INTCON GIE PEIE LCDCON LCDEN SLPEN LCDCST — — LCDDATA0 SEG7 SEG6 COM0 COM0 LCDDATA1 SEG15 SEG14 COM0 COM0 LCDDATA3 SEG7 SEG6 COM1 COM1 LCDDATA4 SEG15 SEG14 COM1 COM1 ...
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... NC RJ11-6PIN ® To MPLAB ICD 2 ® The MPLAB ICD 2 produces a V Note: voltage greater than the maximum V specification of the PIC16LF1902/3. 2011 Microchip Technology Inc. Some programmers produce V (9.0V), an external circuit is required to limit the V voltage. See Figure 19-1 to the Specification” ...
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... Low-Voltage Programming Entry Mode The Low-Voltage Programming Entry mode allows the PIC16LF1902/3 devices to be programmed using V only, without high voltage. When the LVP bit of Configuration Word 2 is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘ ...
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... See Figure 19-4 information. FIGURE 19-4: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING External Programming Signals Data Clock 2011 Microchip Technology Inc. PIC16LF1902/3 for more Normal Connections Isolation devices (as required). * Preliminary Device to be Programmed V DD MCLR ...
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... PIC16LF1902/3 NOTES: DS41455B-page 182 Preliminary 2011 Microchip Technology Inc. ...
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... MHz. All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. 2011 Microchip Technology Inc. PIC16LF1902/3 20.1 Read-Modify-Write Operations Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation ...
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... PIC16LF1902/3 FIGURE 20-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations OPCODE d f (FILE #) for destination for destination 7-bit file register address Bit-oriented file register operations OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General ...
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... TABLE 20-3: PIC16LF1902/3 ENHANCED INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ADDWFC f, d Add with Carry W and f ANDWF f, d AND W with f ASRF f, d Arithmetic Right Shift LSLF f, d Logical Left Shift LSRF f, d Logical Right Shift ...
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... PIC16LF1902/3 TABLE 20-3: PIC16LF1902/3 ENHANCED INSTRUCTION SET (CONTINUED) Mnemonic, Description Operands BRA k Relative Branch BRW – Relative Branch with W CALL k Call Subroutine CALLW – Call Subroutine with W GOTO address RETFIE k Return from interrupt RETLW k Return with literal in W RETURN – Return from Subroutine CLRWDT – ...
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... Description: ASRF Syntax: Operands: Operation: Status Affected: Description: f {,d} Preliminary PIC16LF1902/3 AND literal with W [ label ] ANDLW k 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND’ed with the eight-bit literal ‘k’. The result is placed in the W register. ...
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... PIC16LF1902/3 BCF Bit Clear f Syntax: [ label ] BCF f,b 0 f 127 Operands: 0 b (f<b>) Operation: Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. BRA Relative Branch Syntax: [ label ] BRA label [ label ] BRA $+k -256 label - 255 Operands: -256 ...
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... CLRW Operands: None 00h (W) Operation: 1 Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. 2011 Microchip Technology Inc. PIC16LF1902/3 CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None 00h WDT Operation: 0 WDT prescaler, 1 PD ...
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... PIC16LF1902/3 DECFSZ Decrement f, Skip if 0 Syntax: [ label ] DECFSZ f,d 0 f 127 Operands: d ( (destination); Operation: skip if result = 0 Status Affected: None Description: The contents of register ‘f’ are decre- mented. If ‘d’ is ‘ 0 ’, the result is placed in the W register. If ‘d’ is ‘ 1 ’, the result is placed back in register ‘ ...
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... Carry flag. A ‘ 0 ’ is shifted into the MSb. If ‘d’ is ‘ 0 ’, the result is placed ‘d’ is ‘ 1 ’, the result is stored back in register ‘f’. 0 register f 2011 Microchip Technology Inc. PIC16LF1902/3 MOVF Move f Syntax: [ label ] 0 f 127 Operands: d ...
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... PIC16LF1902/3 MOVIW Move INDFn to W Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-- [ label ] MOVIW k[FSRn] n Operands: mm -32 k 31 INDFn W Operation: Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) ...
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... Operands: Operation: Status Affected: Description Words: 10 Cycles: 11 Example: RESET Syntax: Operands: Operation: Status Affected: Description: Preliminary PIC16LF1902/3 No Operation [ label ] NOP None No operation None No operation NOP Load OPTION_REG Register with W [ label ] OPTION None (W) OPTION_REG None Move data from W register to OPTION_REG register. ...
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... PIC16LF1902/3 RETFIE Return from Interrupt Syntax: [ label ] RETFIE k Operands: None TOS PC, Operation: 1 GIE Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction ...
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... Time-out Status bit set. Watchdog Timer and its pres- caler are cleared. The processor is put into Sleep mode with the oscillator stopped. 2011 Microchip Technology Inc. PIC16LF1902/3 SUBLW Subtract W from literal Syntax: [ label ] 0 k 255 Operands (W) ...
Page 196
... PIC16LF1902/3 SWAPF Swap Nibbles in f Syntax: [ label ] SWAPF f,d 0 f 127 Operands: d (f<3:0>) (destination<7:4>), Operation: (f<7:4>) (destination<3:0>) Status Affected: None Description: The upper and lower nibbles of regis- ter ‘f’ are exchanged. If ‘d’ is ‘ 0 ’, the result is placed in the W register. If ‘ ...
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... DD – DIS Preliminary PIC16LF1902/3 + 0.3V {( (V – ...
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... PIC16LF1902/3 FIGURE 21-1: VOLTAGE FREQUENCY GRAPH, -40°C 3.6 2.5 Internal Oscillator 2 Mode 2.0 1 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 21-1 for each Oscillator mode’s supported frequencies. FIGURE 21-2: HFINTOSC FREQUENCY ACCURACY OVER DEVICE V ...
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... DC Characteristics: PIC16LF1902/3-I/E (Industrial, Extended) PIC16LF1902/3 Param. Sym. Characteristic No. Supply Voltage D001 V DD D002 RAM Data Retention Voltage D002A POR Power-on Reset Release Voltage D002B PORR Power-on Reset Rearm Voltage D003 V ADFVR Fixed Voltage Reference Voltage for ADC, Initial Accuracy D003A ...
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... PIC16LF1902/3 21.2 DC Characteristics: PIC16LF1902/3-I/E (Industrial, Extended) PIC16LF1902/3 Param Device Min. No. Characteristics (1, 2) Supply Current ( D010 — — — D011 — — — D012 — — — D013 — — — D014 — — — D015 — — — D016 — — ...