PIC16LF726-E/ML Microchip Technology, PIC16LF726-E/ML Datasheet - Page 48
![14 KB Flash, 16 MHz Int. Osc, NanoWatt XLP 28 QFN 6x6mm TUBE](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16LF726-E/ML
Manufacturer Part Number
PIC16LF726-E/ML
Description
14 KB Flash, 16 MHz Int. Osc, NanoWatt XLP 28 QFN 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.AC164112.pdf
(302 pages)
Specifications of PIC16LF726-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16F72X/PIC16LF72X
4.5.3
The PIE2 register contains the interrupt enable bits, as
shown in Register 4-3.
REGISTER 4-3:
DS41341E-page 48
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-1
bit 0
U-0
—
PIE2 REGISTER
Unimplemented: Read as ‘0’
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
U-0
—
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
W = Writable bit
‘1’ = Bit is set
U-0
—
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
U-0
—
© 2009 Microchip Technology Inc.
x = Bit is unknown
U-0
—
CCP2IE
R/W-0
bit 0
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