PIC18F23K20-E/ML Microchip Technology, PIC18F23K20-E/ML Datasheet - Page 4
![8 KB Enh Flash, 768 RAM, 25 I/O Pb Free, Nanowatt XLP 28 QFN 6x6mm TUBE](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F23K20-E/ML
Manufacturer Part Number
PIC18F23K20-E/ML
Description
8 KB Enh Flash, 768 RAM, 25 I/O Pb Free, Nanowatt XLP 28 QFN 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(456 pages)
3.PIC18F23K20-ISS.pdf
(10 pages)
Specifications of PIC18F23K20-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
PIC18F23/43K20
5. Module: MSSP (SPI Master mode)
6. Module: MSSP (Master I
DS80469C-page 4
In SPI Master mode, if the SSPBUF register is writ-
ten while a byte is actively being transmitted, an
extra clock pulse will be improperly generated at
the end of the transmission. Further writes to the
SSPBUF register will be inhibited although 8 or 9
clock pulses will be generated for each attempted
write. The WCON bit of the SSPCON register is
properly set indicating that a write collision
occurred. However, the write collision condition
can only be cleared by resetting the MSSP mod-
ule. Clear the MSSP by clearing the SSPEN bit of
the SSPCON1 register.
Work around
Use the SSPIF bit of the PIR1 register or the BF bit
of the SSPSTAT register to determine that the
transmission is complete before writing the
SSPBUF register. In the event that a write collision
does occur, use the Slave Select feature to
resynchronize the Slave clock.
Affected Silicon Revisions
PIC18F23/43K20
In Master I
occurs in the middle of an address or data
reception, then the SCL clock stream will continue
endlessly and the RCEN bit of the SSPCON2
register will remain set improperly. When a Start
condition occurs after the improper Stop condition,
then 9 additional clocks will be generated followed
by the RCEN bit going low.
Work around
Use low-impedance pull-ups on the SDA line to
reduce the possibility of noise glitches, which may
trigger an improper Stop event. Use a time-out
event timer to detect the unexpected Stop condi-
tion and resulting stuck RCEN bit. Clear stuck
RCEN bit by clearing SSPEN bit of SSPCON1.
Affected Silicon Revisions
PIC18F23/43K20
A0
A0
X
X
A1
A1
X
X
2
C Receive mode, if a Stop condition
2
C™ mode)
7. Module: EUSART
8. Module: EUSART
9. Module: Data EEPROM Memory
The OERR flag of the RCSTA register is reset only
by clearing the CREN bit of the RCSTA register or
by a device Reset. Clearing the SPEN bit of the
RCSTA register does not clear the OERR flag.
Work around
Clear the OERR flag by clearing the CREN bit
instead of clearing the SPEN bit.
Affected Silicon Revisions
PIC18F23/43K20
In Asynchronous Receive mode, the RCIDL bit of
the BAUDCON register will properly go low when
an invalid Start bit less than 1/16th of a bit time is
received. The RCIDL bit will then properly go high
1/8th of a bit time later. However, if another invalid
Start bit occurs less than 1 bit time after the leading
edge of the first invalid Start bit then the RCIDL bit
will improperly stay high then improperly go low
one bit time later. The RCIDL bit will then stay low
improperly until a valid Start bit is received.
Work around
When monitoring the RCIDL bit, measure the
length of time between the RCIDL going low and
the RCIF flag going high. If this time is greater than
one character time then restore the RCIDL bit by
resetting the EUSART module. The EUSART
module is reset when the SPEN bit of the RCSTA
register is cleared.
Affected Silicon Revisions
PIC18F23/43K20
The write/erase endurance of Data EE Memory is
limited to 10K cycles.
Work around
Use error correction method that stores data in
multiple locations.
Affected Silicon Revisions
PIC18F23/43K20
A0
A0
A0
X
X
X
A1
A1
A1
X
X
X
2010 Microchip Technology Inc.