PIC18F25K80T-I/MM Microchip Technology, PIC18F25K80T-I/MM Datasheet - Page 263
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PIC18F25K80T-I/MM
Manufacturer Part Number
PIC18F25K80T-I/MM
Description
ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F25K80T-I/MM
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18F25K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3648 B
Interface Type
I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F25K80T-I/MM
Manufacturer:
MICROCHIP
Quantity:
3 000
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19.2
In Capture mode, the CCPRxH:CCPRxL register pair
captures the 16-bit value of the Timer register selected
in the CCPTMRS when an event occurs on the CCPx
pin. An event is defined as one of the following:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
The event is selected by the mode select bits,
CCPxM<3:0> (CCPxCON<3:0>). When a capture is
made, the interrupt request flag bit, CCPxIF (PIR4<x>),
is set; it must be cleared in software. If another capture
occurs before the value in CCPRx is read, the old
captured value is overwritten by the new captured
value.
Figure 19-1
FIGURE 19-1:
2011 Microchip Technology Inc.
Note:
Note:
Capture Mode
For CCP2 only, the Capture mode can use
the CCP2 input pin as the capture trigger
for CCP2 or the input can function as a
time-stamp through the CAN module. The
CAN module provides the necessary
control and trigger signals.
shows the Capture mode block diagram.
CCP3 Pin
CCP4 Pin
This block diagram uses CCP3 and CCP4, and their appropriate timers as an example. For details on all of
the CCP modules and their timer assignments, see
CAPTURE MODE OPERATION BLOCK DIAGRAM
CCP3CON<3:0>
CCP4CON<3:0>
Prescaler
1, 4, 16
Prescaler
1, 4, 16
Q1:Q4
4
Edge Detect
Edge Detect
4
4
and
and
Preliminary
Set CCP4IF
Set CCP3IF
PIC18F66K80 FAMILY
C4TSEL
C3TSEL
C3TSEL
C4TSEL
Table
19.2.1
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
19.2.2
For the available timers (1/3) to be used for the capture
feature, the used timers must be running in Timer mode
or Synchronized Counter mode. In Asynchronous
Counter mode, the capture operation may not work.
The timer to be used with each CCP module is selected
in the CCPTMRS register. (See
Modules and Timer Resources”
Details of the timer assignments for the CCP modules
are given in
19-2.
CCP PIN CONFIGURATION
TIMER1/3 MODE SELECTION
Table
19-2.
TMR3
Enable
TMR1
Enable
TMR3
Enable
TMR1
Enable
CCPR3H
CCPR4H
TMR3H
TMR1H
TMR3H
TMR1H
CCPR3L
CCPR4L
Section 19.1.1 “CCP
.)
TMR1L
TMR3L
TMR3L
TMR1L
DS39977C-page 263
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