PIC18F44K20-E/MV Microchip Technology, PIC18F44K20-E/MV Datasheet - Page 123
![16KB, Flash, 768bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm TU](/photos/16/15/161538/qfn-40_sml.jpg)
PIC18F44K20-E/MV
Manufacturer Part Number
PIC18F44K20-E/MV
Description
16KB, Flash, 768bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm TU
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K20T-ISS.pdf
(456 pages)
Specifications of PIC18F44K20-E/MV
Processor Series
PIC18
Core
PIC18F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
8 KB
Data Ram Size
512 B
Interface Type
I2C, SPI, SCI, USB, MSSP, RJ11
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
35
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
UQFN-40
Development Tools By Supplier
MPLAB Integrated Development Environment
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
Details
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- Download datasheet (4Mb)
TABLE 10-1:
TABLE 10-2:
2010 Microchip Technology Inc.
PORTA
LATA
TRISA
ANSEL
SLRCON
CM1CON0
CM2CON0
CVRCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1:
OSC1/CLKIN/RA7
Legend:
Name
2:
Pin
RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
Not implemented on PIC18F2XK20 devices.
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TRISA7
LATA7
ANS7
CVREN
RA7
C1ON
C2ON
Bit 7
PORTA I/O SUMMARY (CONTINUED)
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
—
Function
(1)
CLKIN
OSC1
(2)
(1)
RA7
(1)
TRISA6
LATA6
ANS6
CVROE
C1OUT
C2OUT
RA6
Bit 6
—
Setting
TRIS
(1)
(2)
(1)
0
1
x
x
(1)
PORTA Data Latch Register (Read and Write to Data Latch)
PORTA Data Direction Control Register
ANS5
CVRR
C1OE
C2OE
Bit 5
I/O
RA5
O
I
I
I
—
(2)
Type
ANA
ANA
DIG
TTL
I/O
SLRE
CVRSS
C1POL
C2POL
ANS4
Bit 4
RA4
LATA<7> data output. Disabled in external oscillator modes.
PORTA<7> data input. Disabled in external oscillator modes.
Main oscillator input connection.
Main clock input connection.
(2)
SLRD
CVR3
ANS3
C1SP
C2SP
PIC18F2XK20/4XK20
Bit 3
RA3
(2)
ANS2
SLRC
CVR2
Bit 2
RA2
C1R
C2R
Description
C1CH1
C2CH1
ANS1
SLRB
CVR1
Bit 1
RA1
C1CH0
C2CH0
CVR0
ANS0
SLRA
Bit 0
DS41303G-page 123
RA0
on page
Values
Reset
62
62
62
62
63
62
62
61
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