PIC18F45K20T-I/PT Microchip Technology, PIC18F45K20T-I/PT Datasheet - Page 24

• Manufacturer Part Number: PIC18F45K20T-I/PT
• Description: 32KB, Flash, 1536bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 44 TQFP 10x10x1mm T
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K20T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240313 - BOARD DEMO 8BIT XLPAC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPDM164124 - KIT STARTER FOR PIC18F4XK20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F45K20T-I/PTTR

PIC18F2XK20/4XK20
4.0
4.1
Code memory is accessed one byte at a time via the
4-bit command, ‘1001’ (table read, post-increment).
The contents of memory pointed to by the Table Pointer
(TBLPTRU:TBLPTRH:TBLPTRL) are serially output on
PGD.
The 4-bit command is shifted in LSb first. The read is
executed during the next 8 clocks, then shifted out on
PGD during the last 8 clocks, LSb to MSb. A delay of
P6 must be introduced after the falling edge of the 8th
TABLE 4-1:
FIGURE 4-1:
DS41297F-page 24
Step 1: Set Table Pointer
0000
0000
0000
0000
0000
0000
Step 2: Read memory and then shift out on PGD, LSb to MSb
1001
PGC
Command
PGD
Note 1:
4-bit
READING THE DEVICE
Read Code Memory, ID Locations
and Configuration Bits
Magnification of the high-impedance delay between PGC and PGD is shown in Figure 4-6.
1
1
READ CODE MEMORY SEQUENCE
2
0
0E <Addr[21:16]>
0E <Addr[15:8]>
0E <Addr[7:0]>
Data Payload
3
TABLE READ POST-INCREMENT INSTRUCTION TIMING DIAGRAM (1001)
0
4
6E F8
6E F7
6E F6
00 00
1
P5
PGD = Input
1
2
3
MOVLW Addr[21:16]
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
TBLRD *+
4
Advance Information
5
6
7
8
P6
PGC of the operand to allow PGD to transition from an
input to an output. During this time, PGC must be held
low (see Figure 4-1). This operation also increments
the Table Pointer by one, pointing to the next byte in
code memory for the next read.
This technique will work to read any memory in the
000000h to 3FFFFFh address space, so it also applies
to the reading of the ID and Configuration registers.
9
LSb
Note:
P14
10
1
Core Instruction
11
2
PGD = Output
When table read protection is enabled, the
first read access to a protected block
should be discarded and the read repeated
to retrieve valid data. Subsequent reads of
the same block can be performed normally.
12
Shift Data Out
3
13
4
14
5
15
© 2009 Microchip Technology Inc.
6
16
MSb
P5A
(Note 1)
Fetch Next 4-bit Command
1
PGD = Input
n
2
n
3
n
4
n