PIC18F6393T-I/PT Microchip Technology, PIC18F6393T-I/PT Datasheet - Page 3

• Manufacturer Part Number: PIC18F6393T-I/PT
• Description: PIC18F With 128-segment LCD Driver And 12-bit ADC, 8KB Flash, 768B RAM, CCP, MSS
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6393T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: AUSART, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM163030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F6393T-I/PTTR

Silicon Errata Issues
1. Module: Master Synchronous Serial Port
2. Module: Master Synchronous Serial Port
 2009 Microchip Technology Inc.
Note:
Configured in SPI slave mode, the MSSP will
generate a write collision if SSPBUF is updated
and the previous SSPBUF contents have not been
transferred to the shift register.
Reinitializing the MSSP – by clearing and setting
the SSPEN bit (SSPCON1<5>) prior to rewriting
SSPBUF – will not prevent the error condition.
Work around
Prior to updating the SSPBUF register with a new
value, verify that the previous contents have been
transferred by reading the BF bit (SSPSTAT<0>).
If the previous byte has not been transferred:
• Update SSPBUF
• If necessary, clear the WCOL bit
Affected Silicon Revisions
In SPI mode, the Buffer Full flag (BF bit in the
SSPSTAT register), the Write Collision Detect bit
(WCOL in SSPCON1) and the Receive Overflow
Indicator bit (SSPOV in SSPCON1) are not reset
upon disabling the SPI module (by clearing the
SSPEN bit in the SSPCON1 register).
For example, if SSPBUF is full (BF bit is set) and
the MSSP module is disabled and re-enabled, the
BF bit will remain set. In SPI Slave mode, a sub-
sequent write to SSPBUF will result in a write
collision. Also, if a new byte is received, a receive
overflow will occur.
C0
(SSPCON1<7>)
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (C1).
C1
X
(MSSP)
(MSSP) – Serial Peripheral
Interface (SPI)
PIC18F6393/6493/8393/8493
3. Module: Master Synchronous Serial Port
4. Module: MSSP – I
Work around
If the buffer is full, before disabling the MSSP
module, ensure that:
• SSPBUF is read (thus clearing the BF flag)
• WCOL is clear
If the module is configured in SPI Slave mode,
ensure that the SSPOV bit is clear before disabling
the module.
Affected Silicon Revisions
In 10-Bit Slave mode, the I
work correctly.
Work around
None.
Affected Silicon Revisions
When configured for I
MSSP module may not receive the correct data,
in extremely rare cases. This occurs only if the
Serial
(SSPBUF) is not read within a window after the
SSPIF interrupt (PIR1<3>) has occurred.
Work around
The issue can be resolved in either one of these
ways:
• Prior to the I
• Each time the SSPIF is set, read the SSPBUF
Affected Silicon Revisions
C0
C0
C0
clock stretching feature.
This
(SSPCON2<0>).
before the first rising clock edge of the next
byte being received.
X
X
X
C1
C1
C1
X
X
X
Receive/Transmit
is
(MSSP) – I
done
2
C slave reception, enable the
by
2
C
2
2
C™
C slave reception, the
setting
2
C™ mode does not
Buffer
DS80347B-page 3
the
Register
SEN
bit