PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet

16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R

PIC18F64J11T-I/PT

Manufacturer Part Number
PIC18F64J11T-I/PT
Description
16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
51
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC18F64J11T-I/PTTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F64J11T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
The PIC18F85J11 family Rev. A4 parts you have
received conform functionally to the Device Data Sheet
(DS39774C), except for the anomalies described
below. Any Data Sheet Clarification issues related to
the PIC18F85J11 family will be reported in a separate
Data Sheet errata. Please check the Microchip web site
for any existing issues.
The
PIC18F85J11 family devices with these Device/
Revision IDs:
All of the issues listed here will be addressed in future
revisions of the PIC18F85J11 family silicon.
1. Module: Reset
© 2008 Microchip Technology Inc.
The Device IDs (DEVID1 and DEVID2) are located at
addresses
configuration space. They are shown in binary in the
format “DEVID2 DEVID1”.
Part Number
PIC18F63J11
PIC18F64J11
PIC18F65J11
PIC18F83J11
PIC18F84J11
PIC18F85J11
When a Brown-out Reset (BOR) occurs and the
BOR bit is reset, the Power-on Reset (POR) bit
also may be reset. The resulting state matches
that of the RCON register following a Power-on
Reset event.
Consequently, an application may not be able to
detect whether a BOR or POR event has occurred.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
following
3FFFFEh:3FFFFFh
PIC18F85J11 Family Rev. A4 Silicon Errata
silicon
0011 1001 000
0011 1001 001
0011 1001 100
0011 1001 101
0011 1001 011
0011 1001 111
Device ID
errata apply
in
the
Revision ID
PIC18F85J11 FAMILY
0 0100
0 0100
0 0100
0 0100
0 0100
0 0100
only
device’s
to
2. Module: MSSP (I
3. Module: MSSP (I
When configured for I
MSSP module may not receive the correct data, in
extremely rare cases. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPBUF) is not
read within a window after the SSPIF interrupt
(PIR1<3>) has occurred.
Work around
The issue can be resolved either of these ways:
• Prior to the I
• Each time the SSPIF is set, read the SSPBUF
Date Codes that pertain to this issue:
All engineering and production devices.
When in I
clock stretching, the first clock pulse after the slave
releases the SCL line may be narrower than the
configured clock width. This may result in the slave
missing the first clock in the next transmission/
reception.
Work around
The clock pulse will be the normal width if the slave
does not perform clock stretching.
Date Codes that pertain to this issue:
All engineering and production devices.
clock stretching feature.
This
(SSPCON2<0>).
before the first rising clock edge of the next byte
being received.
is
2
C Master mode, if the slave performs
done
2
C slave reception, enable the
2
2
by
C™ Slave)
C™ Master)
2
C™ slave reception, the
setting
DS80423A-page 1
the
SEN
bit

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PIC18F64J11T-I/PT Summary of contents

Page 1

... BOR or POR event has occurred. Work around None. Date Codes that pertain to this issue: All engineering and production devices. © 2008 Microchip Technology Inc. PIC18F85J11 FAMILY 2. Module: MSSP (I When configured for I MSSP module may not receive the correct data, in extremely rare cases ...

Page 2

... Disable the EUSART (RCSTA<7> = 0). 3. Re-enable the EUSART (RCSTA<7> = 1). 4. Re-enable receive interrupts (PIE1<5> = 1). (This is the first T delay Execute a NOP instruction. (This is the second T delay.) CY Date Codes that pertain to this issue: All engineering and production devices. DS80423A-page 2 (RCIE bit, © 2008 Microchip Technology Inc. ...

Page 3

... REVISION HISTORY Rev A Document (11/2008) Initial release of this errata. Includes silicon issues 2 1 (Reset), 2 (MSSP – Slave), 3 (MSSP – I Master) and 4 (Enhanced Universal Synchronous Asynchronous Receiver Transmitter – EUSART). © 2008 Microchip Technology Inc. PIC18F85J11 FAMILY 2 C DS80423A-page 3 ...

Page 4

... PIC18F85J11 FAMILY NOTES: DS80423A-page 4 © 2008 Microchip Technology Inc. ...

Page 5

... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 6

... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...

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