PIC18F65K80-E/PT Microchip Technology, PIC18F65K80-E/PT Datasheet - Page 237

• Manufacturer Part Number: PIC18F65K80-E/PT
• Description: ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 64 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K80-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Processor Series: PIC18F65K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 16-5:
16.5.5
When Timer3 gate value status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T3GVAL bit (T3GCON<2>).
The T3GVAL bit is valid even when the Timer3 gate is
not enabled (TMR3GE bit is cleared).
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TMR3GIF
TMR3GE
T3GSPM
T3DONE
T3GPOL
T3GGO/
T3GVAL
T3G_IN
T3GTM
Timer3
T3CKI
TIMER3 GATE VALUE STATUS
TIMER3 GATE SINGLE PULSE AND TOGGLE COMBINED MODE
N
Cleared by Software
Set by Software
Counting Enabled on
Rising Edge of T3G
Preliminary
N + 1
PIC18F66K80 FAMILY
Falling Edge of T3GVAL
N + 2
16.5.6
When the Timer3 gate event interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of T3GVAL
occurs, the TMR3GIF flag bit in the PIR2 register will be
set. If the TMR3GIE bit in the PIE2 register is set, then
an interrupt will be recognized.
The TMR3GIF flag bit operates even when the Timer3
gate is not enabled (TMR3GE bit is cleared).
Set by Hardware on
N + 3
TIMER3 GATE EVENT INTERRUPT
N + 4
Cleared by Hardware on
Falling Edge of T3GVAL
DS39977C-page 237
Cleared by
Software