PIC18F65K80T-I/PT Microchip Technology, PIC18F65K80T-I/PT Datasheet - Page 76

• Manufacturer Part Number: PIC18F65K80T-I/PT
• Description: ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K80T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F65K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F66K80 FAMILY
REGISTER 4-2:
DS39977C-page 76
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
PSPMD
R/W-0
(1)
Unimplemented on devices with 28-pin devices (PIC18F2XK80, PIC18LF2XK80).
PSPMD: Peripheral Module Disable bit
1 = The PSP module is disabled. All PSP registers are held in Reset and are not writable.
0 = The PSP module is enabled
CTMUMD: PMD CTMU Disable bit
1 = The CTMU module is disabled. All CTMU registers are held in Reset and are not writable.
0 = The CTMU module is enabled
ADCMD: ADC Module Disable bit
1 = The ADC module is disabled. All ADC registers are held in Reset and are not writable.
0 = The ADC module is enabled
TMR4MD: TMR4MD Disable bit
1 = The Timer4 module is disabled. All Timer4 registers are held in Reset and are not writable.
0 = The Timer4 module is enabled
TMR3MD: TMR3MD Disable bit
1 = The Timer3 module is disabled. All Timer3 registers are held in Reset and are not writable.
0 = The Timer3 module is enabled
TMR2MD: TMR2MD Disable bit
1 = The Timer2 module is disabled. All Timer2 registers are held in Reset and are not writable.
0 = The Timer2 module is enabled
TMR1MD: TMR1MD Disable bit
1 = The Timer1 module is disabled. All Timer1 registers are held in Reset and are not writable.
0 = The Timer1 module is enabled
TMR0MD: Timer0 Module Disable bit
1 = The Timer0 module is disabled. All Timer0 registers are held in Reset and are not writable.
0 = The Timer0 module is enabled
CTMUMD
R/W-0
PMD1: PERIPHERAL MODULE DISABLE REGISTER 1
W = Writable bit
‘1’ = Bit is set
ADCMD
R/W-0
TMR4MD
R/W-0
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TMR3MD
R/W-0
TMR2MD
R/W-0
 2011 Microchip Technology Inc.
x = Bit is unknown
TMR1MD
R/W-0
TMR0MD
R/W-0
bit 0