PIC18F65K90-E/PT Microchip Technology, PIC18F65K90-E/PT Datasheet
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PIC18F65K90-E/PT
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PIC18F65K90-E/PT Summary of contents
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... Microcontrollers with LCD Driver and 2009-2011 Microchip Technology Inc. PIC18F87K90 Family Data Sheet 64/80-Pin, High-Performance nanoWatt XLP Technology DS39957D ...
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... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009-2011, Microchip Technology Incorporated, Printed in the U ...
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... Multiple LCD timing sources available - Up to four commons: static, 1/2, 1/3 or 1/4 multiplex - Bias configuration: Static, 1/2 or 1/3 • Low-Power Resistor Bias Network for LCD Flash SRAM Program Data EEPROM Device Memory Memory (Bytes) (Bytes) PIC18F65K90 32K 2K PIC18F66K90 64K 4K PIC18F67K90 128K 4K PIC18F85K90 32K 2K PIC18F86K90 64K 4K ...
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... Two Pins • In-Circuit Debug via Two Pins • Programmable: - BOR - LVD • Two Enhanced Addressable USART modules: - LIN/J2602 support - Auto-Baud Detect (ABD) • 12-Bit A/D Converter with Channels: - Auto-acquisition and Sleep operation - Differential Input mode of operation 2009-2011 Microchip Technology Inc. ...
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... RF6/AN11/SEG24/C1INA RF5/AN10/CV /SEG23/C1INB REF RF4/AN9/SEG22/C2INA RF3/AN8/SEG21/C2INB/CTMUI RF2/AN7/C1OUT/SEG20 Note 1: The ECCP2 pin placement depends on the CCP2MX Configuration bit setting. 2: Not available on the PIC18F65K90 and PIC18F85K90. For the QFN package recommended that the bottom pad be connected 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY ...
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... REF RF4/AN9/SEG22/C2INA RF3/AN8/SEG21/C2INB/CTMUI RF2/AN7/C1OUT/SEG20 (3) RH7/SEG43/CCP6 /P1B/AN15 RH6/SEG42/CCP7 (3) /P1C/AN14/C1INC Note 1: The ECCP2 pin placement depends on the CCP2MX Configuration bit setting. 2: Not available on the PIC18F65K90 and PIC18F85K90. 3: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting DS39957D-page 6766 ...
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... Appendix A: Revision History............................................................................................................................................................. 553 Appendix B: Migration From PIC18F85J90 and PIC18F87J90 to PIC18F87K90 .............................................................................. 553 Index ................................................................................................................................................................................................. 555 The Microchip Web Site ..................................................................................................................................................................... 567 Customer Change Notification Service .............................................................................................................................................. 567 Customer Support .............................................................................................................................................................................. 567 Reader Response .............................................................................................................................................................................. 568 Product Identification System ............................................................................................................................................................ 569 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY DS39957D-page 7 ...
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... PIC18F87K90 FAMILY NOTES: DS39957D-page 8 2009-2011 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F65K90 • PIC18F85K90 • PIC18F66K90 • PIC18F86K90 • PIC18F67K90 • PIC18F87K90 This family combines the traditional advantages of all PIC18 microcontrollers – namely, high computational performance and a rich feature set – with a versatile on-chip LCD driver, while maintaining an extremely competitive price point ...
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... Devices in the PIC18F87K90 family are available in 64-pin and 80-pin packages. Block diagrams for the two groups are shown in The devices are differentiated from each other in these ways: • Flash Program Memory: - PIC18FX5K90 (PIC18F65K90 and PIC18F85K90) – 32 Kbytes - PIC18FX6K90 (PIC18F66K90 and PIC18F86K90) – 64 Kbytes - PIC18FX7K90 (PIC18F67K90 and PIC18F87K90) – ...
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... Comparators CTMU RTCC Capture/Compare/PWM (CCP) Modules Enhanced CCP (ECCP) Modules Serial Communications 12-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY PIC18F65K90 PIC18F66K90 DC – 64 MHz 32K 64K 16,384 32,768 Ports 132 (33 SEGs x 4 COMs) ...
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... See Table 1-3 for I/O port pin descriptions. Note 1: RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section 3.0 “Oscillator 2: Configurations”. Unimplemented in the PIC18F65K90. 3: DS39957D-page 12 Data Bus<8> Data Latch 8 8 Data Memory ...
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... I/O port pin descriptions. Note 1: RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section 3.0 “Oscillator Configurations” for 2: more information. Unimplemented in the PIC18F85K90. 3: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY Data Bus<8> Data Latch 8 8 Data Memory ...
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... I C™ C/SMBus Default assignment for ECCP2 when the CCP2MX Configuration bit is set. Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K90 and PIC18F85K90 devices. 3: DS39957D-page 14 Pin Buffer Type Type Master Clear (input) or programming voltage (input). ...
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... I C™ C/SMBus Default assignment for ECCP2 when the CCP2MX Configuration bit is set. Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K90 and PIC18F85K90 devices. 3: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port ...
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... I C™ C/SMBus Default assignment for ECCP2 when the CCP2MX Configuration bit is set. Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K90 and PIC18F85K90 devices. 3: DS39957D-page 16 Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs ...
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... I C™ C/SMBus Default assignment for ECCP2 when the CCP2MX Configuration bit is set. Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K90 and PIC18F85K90 devices. 3: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port ...
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... I C™ C/SMBus Default assignment for ECCP2 when the CCP2MX Configuration bit is set. Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K90 and PIC18F85K90 devices. 3: DS39957D-page 18 Pin Buffer Type Type PORTD is a bidirectional I/O port. I/O ST Digital I/O ...
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... I C™ C/SMBus Default assignment for ECCP2 when the CCP2MX Configuration bit is set. Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K90 and PIC18F85K90 devices. 3: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port ...
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... I C™ C/SMBus Default assignment for ECCP2 when the CCP2MX Configuration bit is set. Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K90 and PIC18F85K90 devices. 3: DS39957D-page 20 Pin Buffer Type Type PORTF is a bidirectional I/O port. I/O ST Digital I/O ...
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... I C™ C/SMBus Default assignment for ECCP2 when the CCP2MX Configuration bit is set. Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K90 and PIC18F85K90 devices. 3: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port ...
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... Default assignment for ECCP2 when the CCP2MX Configuration bit is set. Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K90 and PIC18F85K90 devices. 3: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 4: ...
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... Default assignment for ECCP2 when the CCP2MX Configuration bit is set. Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K90 and PIC18F85K90 devices. 3: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 4: ...
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... Default assignment for ECCP2 when the CCP2MX Configuration bit is set. Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K90 and PIC18F85K90 devices. 3: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 4: ...
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... Default assignment for ECCP2 when the CCP2MX Configuration bit is set. Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K90 and PIC18F85K90 devices. 3: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 4: ...
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... Default assignment for ECCP2 when the CCP2MX Configuration bit is set. Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K90 and PIC18F85K90 devices. 3: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 4: ...
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... Default assignment for ECCP2 when the CCP2MX Configuration bit is set. Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K90 and PIC18F85K90 devices. 3: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 4: ...
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... Default assignment for ECCP2 when the CCP2MX Configuration bit is set. Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K90 and PIC18F85K90 devices. 3: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 4: ...
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... Default assignment for ECCP2 when the CCP2MX Configuration bit is set. Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K90 and PIC18F85K90 devices. 3: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 4: ...
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... Default assignment for ECCP2 when the CCP2MX Configuration bit is set. Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K90 and PIC18F85K90 devices. 3: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 4: ...
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... Default assignment for ECCP2 when the CCP2MX Configuration bit is set. Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K90 and PIC18F85K90 devices. 3: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 4: ...
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... Default assignment for ECCP2 when the CCP2MX Configuration bit is set. Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K90 and PIC18F85K90 devices. 3: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 4: ...
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... Default assignment for ECCP2 when the CCP2MX Configuration bit is set. Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 2: Not available on PIC18F65K90 and PIC18F85K90 devices. 3: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting. 4: ...
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... PIC18F87K90 FAMILY NOTES: DS39957D-page 34 2009-2011 Microchip Technology Inc. ...
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... REF reference for analog modules is implemented The AV and AV pins must always be Note connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY FIGURE 2- MCLR Pin”) ...
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... The DD may be beneficial. A typical Figure 2-1. Other circuit ) and fast signal transitions must IL (Figure 2-2). is replaced for normal run-time EXAMPLE OF MCLR PIN CONNECTIONS R1 R2 MCLR PIC18FXXKXX JP C1 and V specifications are met and V specifications are met. IL 2009-2011 Microchip Technology Inc. ...
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... Panasonic ECJ-4YB1C106K Murata GRM32DR71C106KA01L Murata GRM31CR61C106KC31L 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY Some PIC18FXXKXX families, or some devices within a family, do not provide the option of enabling or disabling the on-chip voltage regulator: • Some devices (with the name, PIC18LFXXKXX) permanently disable the voltage regulator. ...
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... Channel Select” (i.e., PGCx/PGDx pins), programmed into the device, matches the physical connections for the ICSP to the Microchip debugger/emulator tool. For more information on available development tools connection requirements, refer to Section 30.0 “Development Support”. 2009-2011 Microchip Technology Inc Microchip ...
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... Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ kΩ resistor unused pins and drive the SS output to logic low. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY FIGURE 2-5: (refer to Single-Sided and In-Line Layouts: Copper Pour ...
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... PIC18F87K90 FAMILY NOTES: DS39957D-page 40 2009-2011 Microchip Technology Inc. ...
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... When the RA6 and RA7 pins are not used for an oscil- lator function or CLKOUT function, they are available as general purpose I/Os. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY To optimize power consumption when using EC/HS/ XT/LP/RC as the primary oscillator, the frequency input ...
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... INTSRC MFIOSEL OSC<3:0> Setting 1101 1100 1011 1010 0101 0100 0011 0010 0001 0000 011x 100x (and OSCCON, OSCCON2) Peripherals CPU IDLEN Clock Control SCS<1:0> FOSC<3:0> IRCF<2:0> 2009-2011 Microchip Technology Inc. ...
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... Modifying these bits will cause an immediate clock source switch. 4: INTSRC = OSCTUNE<7> and MFIOSEL = OSCCON2<0>. 5: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY The OSCTUNE register tuning and operation of the internal oscillator block. It also implements the PLLEN bit which controls the operation of the Phase Locked Loop (PLL) (see Frequency Multiplier” ...
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... MF-INTOSC is used in place of HF-INTOSC frequencies of 500 kHz, 250 kHz and 31.25 kHz 0 = MF-INTOSC is not used DS39957D-page 44 (4) U-0 R/W-0 U-0 — SOSCGO — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2009-2011 Microchip Technology Inc. R-x R/W-0 MFIOFS MFIOSEL bit Bit is unknown ...
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... Section 3.4 “External Oscillator The secondary oscillators are external clock sources that are not connected to the OSC1 or OSC2 pin. These sources may continue to operate, even after the controller is placed in a power-managed 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 ...
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... The oscillator design requires the use of a crystal rated for parallel resonant operation. Use of a crystal rated for series resonant Note: operation may give a frequency out of the crystal manufacturer’s specifications. Modes”. Figure 3-2 shows the pin 2009-2011 Microchip Technology Inc. ...
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... Also see the notes following this table information. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY Note 1: Higher capacitance increases the stability of the oscillator but also increases the start-up time. 2: Since each resonator/crystal has its OSC2 own characteristics, the user should ...
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... MHz-16 MHz. EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18F87K90 F /4 OSC2/CLKO OSC Figure 3-6. In EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18F87K90 (HS Mode) OSC2 Open HSPLL and ECPLL Modes 2009-2011 Microchip Technology Inc. ...
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... MHz. If HF-INTOSC is used with the PLL, the input frequency to the PLL should be 8 MHz or 16 MHz (IRCF<2:0> = 111, 110). 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY For MF-INTOSC mode to provide a frequency range of 500 kHz to 31 kHz, INTSRC = 1 and MFIOSEL = 1. ...
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... To compensate, decrement the OSCTUNE or tempera- DD register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow. To compensate, increment the OSCTUNE register. 2009-2011 Microchip Technology Inc. ...
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... For ROSEL (REFOCON<4>), the primary oscillator is only available when configured as a default via the Note 1: FOSC settings (regardless of whether the device is in Sleep mode). 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY The ROSSLP and ROSEL bits (REFOCON<5:4>) con- trol the availability of the reference output during Sleep mode ...
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... POR, while the controller becomes ready to execute instructions. OSC1 Pin At logic low (clock/4 output) Feedback inverter is disabled at quiescent voltage level I/O pin, RA6, direction is controlled by TRISA<7> 2009-2011 Microchip Technology Inc. (PWRT)”. Table 31-10 always (Parameter 38, CSD OSC2 Pin ...
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... IDLEN reflects its value when the SLEEP instruction is executed. Note 1: Includes INTOSC (HF-INTOSC and MG-INTOSC) and INTOSC postscaler, as well as the LF-INTISC source. 2: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY The IDLEN bit (OSCCON<7>) controls CPU clocking, while the SCS<1:0> bits (OSCCON<1:0>) select the clock source ...
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... SOSCRUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up and the SOSC oscillator continues to run. Section 28.4 “Two-Speed Registers”.) Figure 4-1), the primary oscillator 2009-2011 Microchip Technology Inc. ...
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... HF-INTOSC) – there are no distinguishable differences between the PRI_RUN and RC_RUN modes during execution. Entering or exiting RC_RUN mode, however, causes a clock switch delay. Therefore, if the primary clock source is the internal oscillator block, using RC_RUN mode is not recommended. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY n-1 ...
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... OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The LF-INTOSC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. Figure 4-4). When the clock 2009-2011 Microchip Technology Inc. ...
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... PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS<1:0> bits Changed Note1 1024 (approx). These intervals are not shown to scale. OST OSC PLL 2: Clock transition typically occurs within 2-4 T 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY n-1 n (1) Clock Transition OSC ...
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... IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or Sleep mode, a WDT time- out will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits (1) T PLL OSTS bit Set CSD 31-10) while it becomes ready 2009-2011 Microchip Technology Inc. ...
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... OSC1 CPU Clock Peripheral Clock Program Counter Wake Event 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY 4.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the SOSC oscillator. This mode is entered from SEC_RUN by set- ting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set the IDLEN bit first, then set the SCS< ...
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... PMD bit. There are four PMD registers in the PIC18F87K90 family devices: PMD0, PMD1, PMD2 and PMD3. These registers have bits associated with each module for disabling or enabling a particular peripheral. or eliminating their power 2009-2011 Microchip Technology Inc. ...
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... PMD is disabled for CCP4 bit 0 TMR12MD: TMR12MD Disable bit 1 = PMD is enabled and all TMR12MD clock sources are disabled 0 = PMD is disabled and TMR12MD is enabled Unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90). Note 1: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 CCP7MD CCP6MD CCP5MD U = Unimplemented bit, read as ‘ ...
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... PMD is disabled for Comparator 1 Unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90). Note 1: DS39957D-page 62 R/W-0 R/W-0 R/W-0 (1) TMR6MD TMR5MD CMP3MD U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) R/W-0 R/W-0 CMP2MD CMP1MD bit Bit is unknown 2009-2011 Microchip Technology Inc. ...
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... PMD is enabled and all TMR1MD clock sources are disabled 0 = PMD is disabled and TMR1MD is enabled bit 0 Unimplemented: Read as ‘0’ RTCCMD can only be set to ‘1’ after an EECON2 unlock sequence. Refer to Note 1: Clock and Calendar (RTCC)” 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 (1) TMR4MD ...
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... PMD is enabled for Analog/Digital Converter, disabling all of its clock sources 0 = PMD is disabled for Analog/Digital Converter DS39957D-page 64 R/W-0 R/W-0 R/W-0 UART2MD UART1MD SSP2MD U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2009-2011 Microchip Technology Inc. R/W-0 R/W-0 SSP1MD ADCMD bit Bit is unknown ...
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... WDT timer and postscaler, loses the currently selected clock source (if the Fail-Safe Clock Monitor is enabled) and modifies the IRCF bits in the OSCCON register (if the internal oscillator block is the device clock source). 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY 4.6.3 EXIT BY RESET ...
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... The peripheral can also be configured as a simple programmable temperature sensor. For more information, see AN 879, “Using Note: the Microchip Ultra Low-Power Wake-up Module” (DS00879). 4-9). ULTRA LOW-POWER WAKE-UP INITIALIZATION Low-Voltage Detect (LVD) or 2009-2011 Microchip Technology Inc. ...
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... F12, Table 31-7 also designated as T Execution continues during T 4: The clock source is dependent upon the settings of the SCS (OSCCON<1:0>), IRCF (OSCCON<6:4>) 5: and FOSC (CONFIG1H<3:0>) bits. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY (5) Clock Source Exit Delay LP, XT, HS HSPLL EC, RC ...
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... PIC18F87K90 FAMILY NOTES: DS39957D-page 68 2009-2011 Microchip Technology Inc. ...
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... Detect V DD Brown-out Reset PWRT 32 s PWRT 11-Bit Ripple Counter LF-INTOSC 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY A simplified block diagram of the on-chip Reset circuit is shown in Figure 5.1 RCON Register Device Reset events are tracked through the RCON register (Register register indicate that a specific Reset event has occurred ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39957D-page 70 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2009-2011 Microchip Technology Inc. R/W-0 R/W-0 POR BOR bit Bit is unknown ...
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... Reset depending on which of the trip levels has been set: 1.8V, 2V, 2.7V or 3V. The typical (IB the Low and Medium Power BOR will be 0.75 A and 3 A. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY In Zero-Power BOR (ZPBORMV), the module monitors the V voltage and re-arms the POR at about 2V. ...
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... MCLR is kept low long enough, the PWRT will expire. Bringing MCLR high will begin execution immediately (Figure 5-5). This is useful for testing purposes or for synchronizing more than one PIC18 device operating in parallel PWRT 2009-2011 Microchip Technology Inc. 33 for Figure 5-3, Figure 5-4, all depict ...
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... FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY T PWRT T PWRT , V RISE > 3. PWRT ): CASE 1 ...
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... Table 5-2 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets, and WDT wake-ups. RCON Register ( POR Table 5-1. STKPTR Register BOR STKFUL STKUNF 2009-2011 Microchip Technology Inc. ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: See Table 5-1 for the Reset value for a specific condition. 4: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---u uuuu uuuu uuuu ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: See Table 5-1 for the Reset value for a specific condition. 4: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt uu-u uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuu- uuuu uuuu ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: See Table 5-1 for the Reset value for a specific condition. 4: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu ---u -uuu u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: See Table 5-1 for the Reset value for a specific condition. 4: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-u uuuu uu-u uuuu uuuu uuuu ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: See Table 5-1 for the Reset value for a specific condition. 4: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset ...
Page 84
... PIC18F87K90 FAMILY NOTES: DS39957D-page 84 2009-2011 Microchip Technology Inc. ...
Page 85
... Unimplemented Read as ‘0’ Sizes of memory areas are not to scale. The sizes of program memory areas are enhanced to show detail. Note: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY The data EEPROM, for practical purposes, can be regarded as a peripheral device because it is addressed and accessed through a set of control registers ...
Page 86
... The entire PIC18F87K90 family offers a range of on-chip Flash program memory sizes, from 32 Kbytes (up to 16,384 single-word instructions) to 128 Kbytes (65,536 single-word instructions). • PIC18F65K90 and PIC18F85K90 – 32 Kbytes of Flash memory, storing up to 16,384 single-word instructions • PIC18F66K90 and PIC18F86K90 – 64 Kbytes of ...
Page 87
... TOSH TOSL 00h 1Ah 34h 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers ...
Page 88
... Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. R/W-0 R/W-0 R/W-0 SP4 SP3 SP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) and Instructions POP R/W-0 R/W-0 SP1 SP0 bit Bit is unknown 2009-2011 Microchip Technology Inc. ...
Page 89
... SUB1 RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY 6.1.5 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
Page 90
... Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write Execute INST (PC) Fetch INST ( Execute INST ( Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Example 6-3 Internal Phase Clock Fetch INST ( Flush (NOP) Fetch SUB_1 Execute SUB_1 2009-2011 Microchip Technology Inc. ...
Page 91
... MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
Page 92
... When this instruction executes, it ignores the BSR completely. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. 6-7. 2009-2011 Microchip Technology Inc. ...
Page 93
... BSR value, to access these registers. 2: These addresses are unused for devices with 32 Kbytes of program memory (PIC18FX5K90). For those devices, read these addresses at 00h. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY Data Memory Map ...
Page 94
... This is data RAM which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. (2) From Opcode Mode”. 2009-2011 Microchip Technology Inc. ...
Page 95
... Addresses, EF4h through F5Fh, are also used by SFRs, but are not part of the Access RAM. Users must always load 5: the proper BSR value to access these registers. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY The SFRs can be classified into two sets: those associated with the “ ...
Page 96
... Name Name Addr. CCPR6L EFDh LCDREF CCP6CON EFCh LCDRL CCPR7H EFBh LCDSE5 (3) CCPR7L EFAh LCDSE4 CCP7CON EF9h LCDSE3 TMR4 EF8h LCDSE2 PR4 EF7h LCDSE1 T4CON EF6h LCDSE0 SSP2BUF EF5h LCDPS SSP2ADD EF4h LCDCON SSP2STAT SSP2CON1 2009-2011 Microchip Technology Inc. ...
Page 97
... ANSEL22 This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented. Note 1: Unimplemented in 64-pin devices (PIC18F6XK90). 2: Unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90). 3: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 WERR — ...
Page 98
... CCP9M1 CCP9M0 --00 0000 xxxx xxxx xxxx xxxx CCP8M1 CCP8M0 --00 0000 xxxx xxxx xxxx xxxx CCP3M1 CCP3M0 0000 0000 xxxx xxxx xxxx xxxx P3DC1 P3DC0 0000 0000 PSS3BD1 PSS3BD0 0000 0000 CCP2M1 CCP2M0 0000 0000 xxxx xxxx 2009-2011 Microchip Technology Inc. ...
Page 99
... RA6 This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented. Note 1: Unimplemented in 64-pin devices (PIC18F6XK90). 2: Unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90). 3: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY Bit 5 Bit 4 Bit 3 P2DC5 P2DC4 P2DC3 ...
Page 100
... EEIP — CMP3IP T1GTM T1GSPM T1GGO/ T1GVAL T1DONE SREN CREN ADDEN FERR TXEN SYNC SENDB BRGH 2009-2011 Microchip Technology Inc. Value on Bit 1 Bit 0 POR, BOR RB1 RB0 xxxx xxxx RC1 RC0 xxxx xxxx RD1 RD0 xxxx xxxx RE1 RE0 xxxx xxxx RF1 — ...
Page 101
... Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented. Note 1: Unimplemented in 64-pin devices (PIC18F6XK90). 2: Unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90). 3: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY Bit 5 Bit 4 Bit 3 T3GTM T3GSPM T3GGO/ ...
Page 102
... INT2IF INT1IF 1100 0000 INT3IP RBIP 1111 1111 INT0IF RBIF 0000 000x xxxx xxxx xxxxxxxx 0000 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 ---0 0000 uu-0 0000 0000 0000 0000 0000 ---0 0000 2009-2011 Microchip Technology Inc. ...
Page 103
... Note 1: operand. For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second 2: operand. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY It is recommended, therefore, that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions be used to 6-2, contains alter the STATUS register because these instructions do not affect the bits in the STATUS register ...
Page 104
... EXAMPLE 6-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR FSR0, 100h ; NEXT CLRF POSTINC0 ; Clear INDF ; register then ; inc pointer BTFSS FSR0H All done with ; Bank1? BRA NEXT ; NO, clear next CONTINUE ; YES, continue 2009-2011 Microchip Technology Inc. Stack Pointer ...
Page 105
... FCCh. This means the contents of location, FCCh, will be added to that of the W register and stored back in FCCh. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY are mapped in the SFR space, but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair ...
Page 106
... Enabling the extended instruction set adds five additional two-word commands to the existing PIC18 instruction set: ADDFSR, CALLW, MOVSF, MOVSS and SUBFSR. These instructions are executed as described in Section 6.2.4 “Two-Word Instructions”. 2009-2011 Microchip Technology Inc. ...
Page 107
... Use of the Access Bank (‘a’ • A file address argument that is less than or equal to 5Fh 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the BSR in Direct Addressing 8-bit address in the Access Bank ...
Page 108
... FSR2H F00h Bank 15 F40h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 060h 100h Bank 1 001001da through Bank 14 F00h Bank 15 F40h SFRs FFFh Data Memory 2009-2011 Microchip Technology Inc. 00h 60h Valid Range for ‘f’ FFh ffffffff FSR2L ffffffff ...
Page 109
... F00h BSR. F60h FFFh 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY Remapping the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit = 1) will continue to use Direct Addressing as before. Any Indirect or Indexed ...
Page 110
... PIC18F87K90 FAMILY NOTES: DS39957D-page 110 2009-2011 Microchip Technology Inc. ...
Page 111
... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: The Table Pointer register points to a byte in program memory. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 112
... The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. The EEIF interrupt flag bit (PIR6<4>) is Note: set when the write is complete. It must be cleared in software. When set, Section 28.0 Table Latch (8-bit) TABLAT 2009-2011 Microchip Technology Inc. ...
Page 113
... The RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error Note 1: condition. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-x R/W-0 ...
Page 114
... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TBLPTR<21:6> TABLE READ – TBLPTR<21:0> Memory”. TBLPTRL 0 TABLE WRITE TBLPTR<5:0> 2009-2011 Microchip Technology Inc. ...
Page 115
... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVF WORD_ODD 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY The TBLPTR points to a byte address in program memory space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. ...
Page 116
... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts 2009-2011 Microchip Technology Inc. ...
Page 117
... Clear the CFGS bit to access program memory • Set WREN to enable byte writes 8. Disable the interrupts. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY The long write is necessary for programming the inter- nal Flash. Instruction execution is halted while in a long write cycle. The long write is terminated by the internal ...
Page 118
... TBLWT holding register. ; loop until buffers are full 2009-2011 Microchip Technology Inc. ...
Page 119
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Bit 21 of TBLPTRU allows access to the device Configuration bits. Note 1: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY ; point to Flash program memory ; access Flash program memory ; enable write to memory ...
Page 120
... PIC18F87K90 FAMILY NOTES: DS39957D-page 120 2009-2011 Microchip Technology Inc. ...
Page 121
... EEPROM for read and write operations. EEADRH holds the two MSbs of the address; the upper 6 bits are ignored. The 10-bit range of the pair can address a memory range of 1024 bytes (00h to 3FFh). 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY 8.2 EECON1 and EECON2 Registers Access to the data EEPROM is controlled by two registers: EECON1 and EECON2 ...
Page 122
... When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error Note 1: condition. DS39957D-page 122 R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) 2009-2011 Microchip Technology Inc. R/S-0 R/S bit Bit is unknown ...
Page 123
... BSF INTCON, GIE BCF EECON1, WREN 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, EECON1, EEADRH:EEADR and EEDATA cannot be modified ...
Page 124
... Read current address ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Increment the high address ; Not zero again ; Disable writes ; Enable interrupts information (e.g., program D124 in Table 31-1. 2009-2011 Microchip Technology Inc. ...
Page 125
... EEDATA EEPROM Data Register EECON2 EEPROM Control Register 2 (not a physical register) EECON1 EEPGD CFGS Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — ...
Page 126
... PIC18F87K90 FAMILY NOTES: DS39957D-page 126 2009-2011 Microchip Technology Inc. ...
Page 127
... Unsigned Hardware Multiply Without Hardware Multiply Signed Hardware Multiply Without Hardware Multiply Unsigned Hardware Multiply Without Hardware Multiply Signed Hardware Multiply 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY EXAMPLE 9-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 9-2: MOVF ARG1, W MULWF ARG2 BTFSC ...
Page 128
... RES2 WREG ; RES3 ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products RES2 WREG ; RES3 ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H RES3 ; ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H RES3 2009-2011 Microchip Technology Inc. ...
Page 129
... Individual interrupts can be disabled through their corresponding enable bits. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
Page 130
... IPEN PEIE/GIEL IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP 2009-2011 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...
Page 131
... A mismatch condition will continue to set this bit. Reading PORTB, and then waiting one additional instruction Note 1: cycle, will end the mismatch condition and allow the bit to be cleared. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY Interrupt flag bits are set when an interrupt ...
Page 132
... Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39957D-page 132 R/W-1 R/W-1 R/W-1 INTEDG2 INTEDG3 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2009-2011 Microchip Technology Inc. R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown ...
Page 133
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding Note: enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 ...
Page 134
... R-0 R/W-0 R/W-0 TX1IF SSP1IF TMR1GIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2009-2011 Microchip Technology Inc. should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
Page 135
... TMR3 register overflowed (must be cleared in software TMR3 register did not overflow bit 0 TMR3GIF: TMR3 Gate Interrupt Flag bit 1 = Timer gate interrupt occurred (must be cleared in software timer gate interrupt occurred 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 BCL2IF BCL1IF HLVDIF U = Unimplemented bit, read as ‘ ...
Page 136
... RTCCIF: RTCC Interrupt Flag bit 1 = RTCC interrupt occurred (must be cleared in software RTCC interrupt occurred DS39957D-page 136 R-0 R/W-0 R/W-0 TX2IF CTMUIF CCP2IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2009-2011 Microchip Technology Inc. R/W-0 R/W-0 CCP1IF RTCCIF bit Bit is unknown ...
Page 137
... Compare Mode TMR register compare match occurred (must be cleared in software TMR register compare match occurred PWM Mode Not used in PWM mode. Unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90). Note 1: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 CCP7IF CCP6IF CCP5IF U = Unimplemented bit, read as ‘ ...
Page 138
... Unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90). Note 1: DS39957D-page 138 R/W-0 R/W-0 R/W-0 (1) (1) TMR8IF TMR7IF TMR6IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) (1) R/W-0 R/W-0 TMR5IF TMR4IF bit Bit is unknown 2009-2011 Microchip Technology Inc. ...
Page 139
... CMP2IF: CMP2 Interrupt Flag bit 1 = CMP2 interrupt occurred (must be cleared in software CMP2 interrupt occurred bit 0 CMP1IF: CM1 Interrupt Flag bit 1 = CMP1 interrupt occurred (must be cleared in software CMP1 interrupt occurred 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 U-0 R/W-0 EEIF — ...
Page 140
... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS39957D-page 140 R/W-0 R/W-0 R/W-0 TX1IE SSP1IE TMR1GIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2009-2011 Microchip Technology Inc. R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown ...
Page 141
... Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 BCL2IE BCL1IE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 142
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 R/W-0 CCP7IE CCP6IE CCP5IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) 2009-2011 Microchip Technology Inc. R/W-0 R/W-0 CCP1IE RTCCIE bit Bit is unknown R/W-0 R/W-0 CCP4IE CCP3IE bit 0 ...
Page 143
... Disables the TMR5 overflow interrupt bit 0 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enables the TMR4 to PR4 match interrupt 0 = Disables the TMR4 to PR4 match interrupt Unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90). Note 1: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 (1) (1) ...
Page 144
... Interrupt is enabled 0 = interrupt is disabled bit 0 CMP1IE: CMP1 Enable bit 1 = Interrupt is enabled 0 = interrupt is disabled DS39957D-page 144 R/W-0 U-0 R/W-0 EEIE — CMP3IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2009-2011 Microchip Technology Inc. R/W-0 R/W-0 CMP2IE CMP1IE bit Bit is unknown ...
Page 145
... TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-1 R/W-1 R/W-1 TX1IP SSP1IP TMR1GIP U = Unimplemented bit, read as ‘0’ ...
Page 146
... Low priority bit 0 TMR3GIP: TMR3 Gate Interrupt Priority bit 1 = High priority 0 = Low priority DS39957D-page 146 R/W-1 R/W-1 R/W-1 BCL2IP BCL1IP HLVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2009-2011 Microchip Technology Inc. R/W-1 R/W-1 TMR3IP TMR3GIP bit Bit is unknown ...
Page 147
... Bit is set bit 7-0 CCP10IP:CCP3IP: CCP<10:3> Interrupt Priority bits 1 = High priority 0 = Low priority CCP10IP and CCP9IP are unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90). Note 1: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY R-1 R/W-1 R/W-1 TX2IP CTMUIP CCP2IP U = Unimplemented bit, read as ‘ ...
Page 148
... Unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90). Note 1: DS39957D-page 148 R/W-1 R/W-1 R/W-1 (1) (1) TMR8IP TMR7IP TMR6IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) (1) R/W-1 R/W-1 TMR5IP TMR4IP bit Bit is unknown 2009-2011 Microchip Technology Inc. ...
Page 149
... Low priority bit 1 CMP2IP: CMP2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CMP1IP: CMP1 Interrupt Priority bit 1 = High priority 0 = Low priority 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-1 U-0 R/W-1 EEIP — CMP3IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 150
... BOR: Brown-out Reset Status bit For details of bit operation, see DS39957D-page 150 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Register 5-1. Register 5-1. Register 5-1. Register 5-1. Register 5-1. 2009-2011 Microchip Technology Inc. R/W-0 R/W-0 POR BOR bit Bit is unknown ...
Page 151
... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2<2>). For further details on the Timer0 module, see Section 12.0 “Timer0 Module” ...
Page 152
... TMR3GIF 77 CCP1IF RTCCIF 77 CCP4IF CCP3IF 77 TMR5IF TMR4IF 77 CMP2IF CMP1IF 77 TMR2IE TMR1IE 77 TMR3IE TMR3GIE 77 CCP1IE RTCCIE 77 CCP4IE CCP3IE 77 TMR5IE TMR4IE 77 CMP2IE CMP1IE 80 TMR2IP TMR1IP 77 TMR3IP TMR3GIP 77 CCP1IP RTCCIP 77 CCP4IP CCP3IP 77 TMR5IP TMR4IP 76 CMP2IP CMP1IP 77 PD POR BOR 76 2009-2011 Microchip Technology Inc. ...
Page 153
... PORT I/O pins have diode protection to V Note: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY 11.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V All of the digital ports are 5 ...
Page 154
... USING THE OPEN-DRAIN OUTPUT (USART SHOWN AS EXAMPLE) 3.3V PIC18F67K90 V DD (at logic ‘1’) U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2009-2011 Microchip Technology Inc. +5V 3. U-0 R/W-0 — SSP2OD bit Bit is unknown ...
Page 155
... Open-drain capability is enabled 0 = Open-drain capability is disabled bit 0 CCP3OD: ECCP3 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled Unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90). Note 1: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY R/W-0 R/W-0 R/W-0 CCP7OD CCP6OD CCP5OD U = Unimplemented bit, read as ‘ ...
Page 156
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Setting these registers makes the corresponding pins analog and clearing the registers makes the ports digi- tal. For details on these registers, see “12-Bit Analog-to-Digital Converter (A/D) 2009-2011 Microchip Technology Inc. U-0 R/W-0 — CTMUDS bit Bit is unknown Section 23 ...
Page 157
... RA5 and RA<3:0> are configured as Note: analog inputs on any Reset and are read as ‘0’. RA4 is configured as a digital input. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY OSC2/CLKO/RA6 and OSC1/CLKI/RA7 serve as the external circuit connections for the exter- ...
Page 158
... Main oscillator input connection (HS, XT and LP modes). I ANA Main external clock source input (EC modes). O DIG LATA<7> data output; disabled when OSC2 Configuration bit is set. I TTL PORTA<7> data input; disabled when OSC2 Configuration bit is set. Description /4, EC and INTOSC modes). OSC 2009-2011 Microchip Technology Inc. ...
Page 159
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they Note 1: are disabled and read as ‘x’. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY Bit 5 Bit 4 ...
Page 160
... Timer1 external clock gate input. The RB<5:0> pins also are multiplexed with LCD seg- ment drives that are controlled by bits in the registers, LCDSE1 and LCDSE3. I/O port functionality is only available when the LCD segments are disabled. 2009-2011 Microchip Technology Inc. device from delay. CY ...
Page 161
... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, Legend: TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY I/O I/O ...
Page 162
... TMR0IF TMR0IP INT3IE INT2IE INT1IE INT3IF SE13 SE12 SE11 SE10 SE29 SE28 SE27 SE26 Reset Bit 1 Bit 0 Values on Page: RB1 RB0 78 LATB1 LATB0 78 TRISB1 TRISB0 78 INT0IF RBIF 75 75 INT3IP RBIP INT2IF INT1IF 75 SE09 SE08 83 SE25 SE24 83 2009-2011 Microchip Technology Inc. ...
Page 163
... TRIS bit settings. These pins are configured as digital inputs Note: on any device Reset. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. The RC< ...
Page 164
... Synchronous serial data output (EUSART module); takes priority over port data. DIG Synchronous serial data input (EUSART module); user must configure as an input. ST Synchronous serial clock input (EUSART module). ANA LCD Segment 27 output; disables all other pin functions. Description 2009-2011 Microchip Technology Inc. ...
Page 165
... LCDSE4 SE39 SE38 ODCON1 SSP1OD CCP2OD CCP1OD Legend: Shaded cells are not used by PORTC. This bit is unimplemented in PIC18F6XK90 devices, read as ‘0’. Note 1: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY I/O Type DIG LATC<7> data output. ST PORTC<7> data input. ST Asynchronous serial receive data input (EUSART module). ...
Page 166
... EXAMPLE 11-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs 2009-2011 Microchip Technology Inc. ...
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... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, Legend Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY I/O I/O Type O DIG LATD<0> data output. ...
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... Note 1: DS39957D-page 168 Bit 4 Bit 3 Bit 2 RD4 RD3 RD2 LATD4 LATD3 LATD2 TRISD4 TRISD3 TRISD2 SE04 SE03 SE02 (1) — — RTSECSEL1 RTSECSEL0 Reset Bit 1 Bit 0 Values on Page: RD1 RD0 78 LATD1 LATD0 78 TRISD1 TRISD0 78 SE01 SE00 83 — 80 2009-2011 Microchip Technology Inc. ...
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... Note 1: using the internal resistor ladder, the LCDBIASx pins are also available as I/O ports (RE0, RE1 and RE2). 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY Pins, RE2, RE1 and RE0, are multiplexed with the functions of LCDBIAS3, LCDBIAS2 and LCDBIAS1. When LCD bias generation is required (in any applica- tion where the device is connected to an external LCD), these pins cannot be used as digital I/O ...
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... PORTE<6> data input. O ANA LCD Common 3 output; disables all other outputs. O — ECCP1 PWM Output B. May be configured for tri-state during Enhanced PWM shutdown events. O DIG CCP6 Compare/PWM output; takes priority over port data CCP6 capture input. Description 2009-2011 Microchip Technology Inc. ...
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... CCP8OD CCP7OD CCP6OD PADCFG1 RDPU REPU Legend: Shaded cells are not used by PORTE. This bit is not available in 64-pin devices. Note 1: Unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90). 2: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY I/O I/O Type O DIG LATE<7> data output PORTE< ...
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... Make AN6, AN7 and AN5 digital MOVWF ANCON1 ; MOVLW 0F0h ; Make AN8, AN9, AN10 and AN11 digital MOVWF ANCON2 ; Set PORTF as digital I/O MOVLW 0CEh ; Value used to ; initialize data ; direction MOVWF TRISF ; Set RF3:RF1 as inputs ; RF5:RF4 as outputs ; RF7:RF6 as inputs 2009-2011 Microchip Technology Inc. ...
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... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, Legend: TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY I/O I/O ...
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... CVRR CVRSS CVR3 CVR2 SE21 SE20 SE19 SE18 SE29 SE28 SE27 SE26 Reset Bit 1 Bit 0 Values on Page: RF1 — 78 LATF1 — 78 TRISF1 — 78 ANSEL1 ANSEL0 81 ANSEL8 81 — — 77 CVR1 CVR0 77 SE17 SE16 83 SE25 SE24 83 2009-2011 Microchip Technology Inc. ...
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... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, Legend Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTG pin ...
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... See the MCLR/RG5 pin. Bit 5 Bit 4 Bit 3 Bit 2 (1) RG4 RG3 RG2 — TRISG4 TRISG3 TRISG2 SE28 SE27 SE26 — — — Description Reset Values Bit 1 Bit 0 on Page: RG1 RG0 78 TRISG1 TRISG0 78 SE25 SE24 83 81 — SSP2OD 81 81 2009-2011 Microchip Technology Inc. ...
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... PORTH pins are multiplexed ADC/CCP/Comparator and LCD segment controlled by the LCDSE5 register. I/O port functions are only available when the segments are disabled. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY EXAMPLE 11-8: CLRF PORTH CLRF LATH BANKSEL ANCON2 MOVLW 0Fh MOVWF ...
Page 178
... CCP8 compare/PWM output; takes priority over port data CCP8 capture input. O — ECCP3 PWM Output B. May be configured for tri-state during Enhanced PWM. I ANA A/D Input Channel 13. Default input configuration on POR; does not affect digital input. I ANA Comparator 2 Input D. Description 2009-2011 Microchip Technology Inc. ...
Page 179
... SE46 ANCON1 ANSEL15 ANSEL14 ANCON2 ANSEL23 ANSEL22 (1) (1) ODCON2 CCP10OD CCP9OD Unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90). Note 1: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY I/O I/O Type O DIG LATH<6> data output PORTH<6> data input. O ANA LCD Segment 42 output; disables all other pin functions. ...
Page 180
... Reset. EXAMPLE 11-9: INITIALIZING PORTJ CLRF PORTJ ; Initialize PORTJ by ; clearing output latches CLRF LATJ ; Alternate method ; to clear output latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISJ ; Set RJ3:RJ0 as inputs ; RJ5:RJ4 as output ; RJ7:RJ6 as inputs 2009-2011 Microchip Technology Inc. ...
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... TRISJ5 LCDSE4 SE39 SE38 SE37 PADCFG1 RDPU REPU RJPU Legend: Shaded cells are not used by PORTJ. Unimplemented in PIC18F6XK90 devices, read as ‘0’. Note 1: 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY I/O I/O Type DIG LATJ<0> data output PORTJ<0> data input. I DIG LATJ< ...
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... PIC18F87K90 FAMILY NOTES: DS39957D-page 182 2009-2011 Microchip Technology Inc. ...
Page 183
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY The T0CON register aspects of the module’s operation, including the prescale selection both readable and writable. Figure 12-1 provides a simplified block diagram of the Timer0 module in 8-bit mode ...
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... T Delay There is a delay between OSC 12-2). TMR0H is updated with the Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus 2009-2011 Microchip Technology Inc. ...
Page 185
... INTCON GIE/GIEH PEIE/GIEL TMR0IE T0CON TMR0ON T08BIT Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY 12.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
Page 186
... PIC18F87K90 FAMILY NOTES: DS39957D-page 186 2009-2011 Microchip Technology Inc. ...
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... Stops Timer1 The F clock source should not be selected if the timer will be used with the ECCP capture/compare features. Note 1: OSC 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY Figure 13-1 displays a simplified block diagram of the Timer1 module. The SOSC oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation ...
Page 188
... Timer1 gate pin Programming the T1GCON register prior to T1CON is recommended. Note 1: DS39957D-page 188 (T1GCON), (1) R/W-0 R/W-0 R-x T1GSPM T1GGO/T1DONE T1GVAL U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 T1GSS1 T1GSS0 bit Bit is unknown 2009-2011 Microchip Technology Inc. ...
Page 189
... Microchip Technology Inc. PIC18F87K90 FAMILY 13.3.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. When enabled to count, Timer1 is incremented on the rising edge of the external clock input, T1CKI. Either of these external clock sources can be synchronized to the ...
Page 190
... TMR1ON (2) EN TMR1L T1CLK Q D TMR1CS<1:0> T1SYNC Prescaler OSC T1CKPS<1:0> Internal 01 Clock F /4 OSC Internal 00 Clock 0 T1GVAL Data Bus T1GCON Q1 EN Interrupt Set TMR1GIF det TMR1GE Synchronized 0 Clock Input 1 Synchronize (3) det OSC Sleep Input Internal Clock 2009-2011 Microchip Technology Inc. ...
Page 191
... XTAL 32.768 kHz SOSCO See the Notes with Table 13-2 Note: information about capacitor selection. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY TABLE 13-2: Oscillator Type LP Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stabil- ity of the oscillator, but also increases the start-up time ...
Page 192
... Timer1 interrupt, if enabled, is generated on overflow which is latched in the Timer1 Overflow Interrupt Flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled or disabled by setting or clearing the Timer1 Interrupt Enable bit, TMR1IE (PIE1<0>). OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING OSC1 OSC2 RC0 RC1 RC2 2009-2011 Microchip Technology Inc. ...
Page 193
... TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY 13.8.1 TIMER1 GATE COUNT ENABLE The Timer1 Gate Enable mode is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 Gate Enable mode is configured using the T1GPOL bit (T1GCON<6>). ...
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... CMP1OUT (CMSTAT<5>) bit. 13.8.2.4 Comparator 2 Output Gate Operation The output of Comparator 2 can be internally supplied to the Timer1 gate circuitry. After setting up Comparator 2 with the CM2CON register, Timer1 will increment depending on the transition of the CMP2OUT (CMSTAT<6>) bit. 2009-2011 Microchip Technology Inc. ...
Page 195
... T1G_IN T1CKI T1GVAL Timer1 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY The T1GVAL bit (T1GCON<2>) indicates when the Toggled mode is active and the timer is counting. The Timer1 Gate Toggle mode is enabled by setting the T1GTM bit (T1GCON<5>). When T1GTM is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured ...
Page 196
... The value is stored in the T1GVAL bit (T1GCON<2>). This bit is valid even when the Timer1 gate is not enabled (TMR1GE bit is cleared). Cleared by Hardware on Falling Edge of T1GVAL Set by Hardware on Falling Edge of T1GVAL 2009-2011 Microchip Technology Inc. Figure 13-7.) Cleared by Software ...
Page 197
... OSCCON2 — SOSCRUN CCPTMRS0 C3TSEL1 C3TSEL0 C2TSEL2 C2TSEL1 C2TSEL0 C1TSEL2 C1TSEL1 C1TSEL0 CCPTMRS1 C7TSEL1 C7TSEL0 CCPTMRS2 — — Legend: Shaded cells are not used by the Timer1 module. 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY Set by Hardware on Falling Edge of T1GVAL Bit 5 Bit 4 ...
Page 198
... PIC18F87K90 FAMILY NOTES: DS39957D-page 198 2009-2011 Microchip Technology Inc. ...
Page 199
... T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 2009-2011 Microchip Technology Inc. PIC18F87K90 FAMILY The value of TMR2 is compared to that of the Period reg- ister, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output ...
Page 200
... INT0IE RBIE TMR0IF TX1IF SSP1IF TMR1GIF TX1IE SSP1IE TMR1GIE TX1IP SSP1IP TMR1GIP Section 21.0 Module”. Set TMR2IF TMR2 Output (to PWM or MSSPx) PR2 8 Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 75 TMR2IF TMR1IF 77 TMR2IE TMR1IE 77 TMR2IP TMR1IP 2009-2011 Microchip Technology Inc. ...