PIC18F86J55-I/PT Microchip Technology, PIC18F86J55-I/PT Datasheet - Page 21

• Manufacturer Part Number: PIC18F86J55-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J55-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 96KB (48K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 1-3:
© 2009 Microchip Technology Inc.
RG0/PMA8/ECCP3/P3A
RG1/PMA7/TX2/CK2
RG2/PMA6/RX2/DT2
RG3/PMCS1/CCP4/P3D
RG4/PMCS2/CCP5/P1D
V
V
AV
AV
ENVREG
V
V
Legend: TTL = TTL compatible input
Note 1:
USB
SS
DD
DDCORE
SS
DD
RG0
PMA8
ECCP3
P3A
RG1
PMA7
TX2
CK2
RG2
PMA6
RX2
DT2
RG3
PMCS1
CCP4
P3D
RG4
PMCS2
CCP5
P1D
V
V
DDCORE
CAP
2:
3:
Pin Name
/V
ST = Schmitt Trigger input with CMOS levels
I
P
Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
CAP
= Input
= Power
PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
9, 25, 41, 56
26, 38, 57
64-TQFP
20
19
18
10
17
3
4
5
6
8
Type
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
P
P
P
P
P
P
P
I
I
Buffer
Type
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PORTG is a bidirectional I/O port.
Ground reference for logic and I/O pins.
Positive supply for peripheral digital logic and I/O pins.
Ground reference for analog modules.
Positive supply for analog modules.
Enable for on-chip voltage regulator.
Core logic power or external filter capacitor connection.
USB voltage input pin.
PIC18F87J50 FAMILY
Digital I/O.
Parallel Master Port address.
Capture 3 input/Compare 3 output/PWM3 output.
ECCP3 PWM output A.
Digital I/O.
Parallel Master Port address.
EUSART2 asynchronous transmit.
EUSART2 synchronous clock (see related RX2/DT2).
Digital I/O.
Parallel Master Port address.
EUSART2 asynchronous receive.
EUSART2 synchronous data (see related TX2/CK2).
Digital I/O.
Parallel Master Port chip select 1.
Capture 4 input/Compare 4 output/PWM4 output.
ECCP3 PWM output D.
Digital I/O.
Parallel Master Port chip select 2.
Capture 5 input/Compare 5 output/PWM5 output.
ECCP1 PWM output D.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator
enabled).
CMOS = CMOS compatible input or output
Analog = Analog input
O
OD
= Output
= Open-Drain (no P diode to V
Description
DS39775C-page 21
DD
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