PIC18F96J65-I/PF Microchip Technology, PIC18F96J65-I/PF Datasheet - Page 13
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PIC18F96J65-I/PF
Manufacturer Part Number
PIC18F96J65-I/PF
Description
96KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(8 pages)
3.PIC18F66J65-IPT.pdf
(480 pages)
4.PIC18F66J65-IPT.pdf
(4 pages)
5.PIC18F66J65-IPT.pdf
(10 pages)
6.PIC18F96J60-IPT.pdf
(24 pages)
Specifications of PIC18F96J65-I/PF
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
96KB (48K x 16)
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F96J65-I/PF
Manufacturer:
Microchip
Quantity:
251
Company:
Part Number:
PIC18F96J65-I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
3.2.1
The previous programming example assumed that the
device had been Bulk Erased prior to programming. It
may be the case, however, that the user wishes to
modify only a section of an already programmed
device.
The appropriate number of bytes required for the erase
buffer (1,024 bytes) must be read out of code memory
(as described in Section 4.2 “Verify Code Memory and
Configuration Word”) and buffered. Modifications can
be made on this buffer. Then, the row of code memory
that was read out must be erased and rewritten with the
modified data. The code sequence is shown in Table 3-4.
The WREN bit must be set if the WR bit in EECON1 is
used to initiate a write sequence.
TABLE 3-4:
© 2009 Microchip Technology Inc.
Step 1: Set the Table Pointer for the block to be erased.
Step 2: Enable memory writes and set up an erase.
Step 3: Initiate erase.
Step 4: Load write buffer. The correct bytes will be selected based on the Table Pointer.
Step 5: Repeat Step 4, for a total of 16 times, to completely rewrite the 1024 bytes of the erase buffer.
Step 6: To continue modifying data, repeat Steps 1 through 4, where the Address Pointer is incremented by 1024 bytes at each
iteration of the loop.
Step 7: Disable writes.
Command
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1101
1111
0000
0000
4-Bit
.
.
.
MODIFYING CODE MEMORY
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
84 A6
88 A6
82 A6
00 00
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
<MSB><LSB>
<MSB><LSB>
00 00
94 A6
MODIFYING CODE MEMORY
Data Payload
.
.
.
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BSF
NOP - hold PGC high for time P10.
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
Write 2 bytes and post-increment address by 2.
Repeat write operation 30 more times to fill the write buffer
Write 2 bytes and start programming.
NOP - hold PGC high for time P9.
BCF
<Addr[21:16]>
TBLPTRU
<Addr[8:15]>
TBLPTRH
<Addr[7:0]>
TBLPTRL
EECON1, WREN
EECON1, FREE
EECON1, WR
<Addr[21:16]>
TBLPTRU
<Addr[8:15]>
TBLPTRH
<Addr[7:0]>
TBLPTRL
EECON1, WREN
PIC18F97J60 FAMILY
3.2.2
Since the Flash Configuration Words are stored in
program memory, they are programmed as if they were
program data. Refer to Section 3.2 “Code Memory
Programming” and Section 3.2.1 “Modifying Code
Memory” for methods and examples on programming
or modifying program memory. See also Section 5.0
“Configuration Word” for additional information on
the Configuration Words.
Core Instruction
CONFIGURATION WORD
PROGRAMMING
DS39688D-page 13