PIC18LF14K22-E/ML Microchip Technology, PIC18LF14K22-E/ML Datasheet - Page 240
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PIC18LF14K22-E/ML
Manufacturer Part Number
PIC18LF14K22-E/ML
Description
16KB Flash, 512bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 QFN 4x4mm TUB
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18LF13K22-ISS.pdf
(388 pages)
Specifications of PIC18LF14K22-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
A/d Bit Size
10 bit
A/d Channels Available
12
Height
0.88 mm
Length
4 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.8 V, 2.7 V
Width
4 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F1XK22/LF1XK22
TABLE 19-1:
REGISTER 19-1:
DS41365D-page 240
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
Note 1:
SRCLK
SRLEN
R/W-0
111
110
101
100
011
010
001
000
Changing the SRCLK bits while the SR latch is enabled may cause false triggers to the set and Reset
inputs of the latch.
SRLEN: SR Latch Enable bit
1 = SR latch is enabled
0 = SR latch is disabled
SRCLK<2:0>
000 = 1/4 Peripheral cycle clock
001 = 1/8 Peripheral cycle clock
010 = 1/16 Peripheral cycle clock
011 = 1/32 Peripheral cycle clock
100 = 1/64 Peripheral cycle clock
101 = 1/128 Peripheral cycle clock
110 = 1/256 Peripheral cycle clock
111 = 1/512 Peripheral cycle clock
SRQEN: SR Latch Q Output Enable bit
1 = Q is present on the RA2 pin
0 = Q is internal only
SRNQEN: SR Latch Q Output Enable bit
1 = Q is present on the RC4 pin
0 = Q is internal only
SRPS: Pulse Set Input of the SR Latch bit
1 = Pulse input
0 = Always reads back ‘0’
SRPR: Pulse Reset Input of the SR Latch bit
1 = Pulse input
0 = Always reads back ‘0’
Divider
SRCLK FREQUENCY TABLE
512
256
128
SRCLK2
64
32
16
8
4
R/W-0
SRCON0: SR LATCH CONTROL REGISTER
F
(1)
OSC
W = Writable bit
‘1’ = Bit is set
: SR Latch Clock divider bits
SRCLK1
25.6 s
12.8 s
6.4 s
3.2 s
1.6 s
0.8 s
0.4 s
0.2 s
R/W-0
= 20 MHz
(1)
SRCLK0
F
R/W-0
OSC
Preliminary
0.25 s
0.5 s
32 s
16 s
8 s
4 s
2 s
1 s
= 16 MHz
U = Unimplemented
‘0’ = Bit is cleared
SRQEN
R/W-0
F
OSC
0.5 s
64 s
32 s
16 s
8 s
4 s
2 s
1 s
= 8 MHz F
SRNQEN
R/W-0
OSC
128 s
2010 Microchip Technology Inc.
64 s
32 s
16 s
8 s
4 s
2 s
1 s
= 4 MHz
C = Clearable only bit
x = Bit is unknown
R/W-0
SRPS
F
OSC
512 s
256 s
128 s
64 s
32 s
16 s
8 s
4 s
R/W-0
SRPR
= 1 MHz
bit 0
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