PIC18LF14K50T-I/SO Microchip Technology, PIC18LF14K50T-I/SO Datasheet - Page 6
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PIC18LF14K50T-I/SO
Manufacturer Part Number
PIC18LF14K50T-I/SO
Description
16 KB Flash, 768 RAM, 15 I/O, 10-Bit ADC, USB 2.0, NanoWatt XLP 20 SOIC .300in T
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F13K50-ISS.pdf
(420 pages)
2.PIC18F13K50-ISS.pdf
(40 pages)
3.PIC18F13K50-ISS.pdf
(10 pages)
4.PIC18F13K50-ISS.pdf
(2 pages)
Specifications of PIC18LF14K50T-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, I2C, MSSP, SPI, USB
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF14K50T-I/SO
Manufacturer:
MICROCHIP
Quantity:
12 000
PIC18F1XK50/PIC18LF1XK50
3.0
For the PIC18F14K50/PIC18LF14K50 device, the
program Flash space extends from 0000h to 03FFFh
(16 Kbytes)
PIC18F13K50/PIC18LF13K50 device, the program
Flash space extends from 0000h to 01FFFh (8 Kbytes)
in two 4-Kbyte blocks.
For the PIC18F14K50/PIC18LF14K50 addresses
0000h through 0FFFh, however, define a “Boot Block”
region that is treated separately from Block 0. For the
PIC18F13K50/PIC18LF13K50
through 07FFh, define the “Boot Block” region. All of
these blocks define code protection boundaries within
the program Flash space. The size of the Boot Block in
the PIC18F14K50/PIC18LF14K50 devices can be
configured as 2K, or 4 Kbyte (see Figure 3-1). The size
FIGURE 3-1:
DS41342E-page 6
MEMORY MAPS
Note 1: Boot Block size is determined by the BBSIZ bit in the CONFIG4L register.
in
00FFFFh
100000h
1FFFFFh
two
000000h
MEMORY MAP AND THE PROGRAM FLASH SPACE FOR PIC18F14K50/
PIC18LF14K50 DEVICES
8-Kbyte
Unimplemented
Program Flash
Configuration
Read as ‘0’
and ID
Space
addresses
blocks.
Advance Information
For
0000h
the
Unimplemented
Boot Block*
BBSIZ = 1
Read ‘0’s
Block 0
Block 1
MEMORY SIZE/DEVICE
(PIC18F14K50)
of the Boot Block in the PIC18F13K50/PIC18LF13K50
devices can be configured as 1K, or 2 Kbytes, as
illustrated in Figure 3-1. This is done through the
BBSIZ bit in the Configuration register, CONFIG4L. It is
important to note that increasing the size of the Boot
Block decreases the size of the Block 0.
TABLE 3-1:
PIC18LF13K50
PIC18LF14K50
8 KW
PIC18F13K50/
PIC18F14K50/
Unimplemented
Device
Boot Block
BBSIZ = 0
Read ‘0’s
Block 0
Block 1
(1)
IMPLEMENTATION OF
PROGRAM FLASH
Program Flash Size (Words)
2010 Microchip Technology Inc.
0003FFh
0007FFh
000FFFh
001FFFh
00FFFFh
000000h
000400h
000800h
001000h
002000h
Address
Range
000000h-000FFFh (4K)
000000h-001FFFh (8K)