PIC18LF2458-I/SP Microchip Technology, PIC18LF2458-I/SP Datasheet - Page 30

• Manufacturer Part Number: PIC18LF2458-I/SP
• Description: 24KB Flash, 2KB RAM, 256 Bytes EEPROM, 24 I/O, USB, 12bit ADC 28 SPDIP .300in TU
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2458-I/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 24KB (12K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2458/2553/4458/4553
2.8
An A/D conversion can be started by the Special Event
Trigger of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D acquisition and
conversion, and the Timer1 (or Timer3) counter will be
reset to zero. Timer1 (or Timer3) is reset to automatically
repeat the A/D acquisition period with minimal software
overhead (firmware must move ADRESH:ADRESL to
TABLE 2-2:
DS39887C-page 30
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTA
TRISA
PORTB
TRISB
LATB
PORTE
TRISE
LATE
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1:
Name
(1)
2:
3:
4:
(1)
(1)
Use of the CCP2 Trigger
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’.
RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator configuration;
otherwise, they are read as ‘0’.
RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
For these Reset values, see the “PIC18F2455/2550/4455/4550 Data Sheet”.
PORTB Data Direction Control Register
PORTB Data Latch Register (Read and Write to Data Latch)
GIE/GIEH PEIE/GIEL TMR0IE
A/D Result Register High Byte
A/D Result Register Low Byte
SPPIE
SPPIP
SPPIF
OSCFIF
OSCFIE
OSCFIP
ADFM
RDPU
Bit 7
RB7
—
—
—
—
—
—
REGISTERS ASSOCIATED WITH A/D OPERATION
(1)
(1)
(1)
TRISA6
RA6
CMIE
CMIP
CMIF
ADIF
ADIE
ADIP
Bit 6
RB6
—
—
—
—
—
—
(2)
(2)
PORTA Data Direction Control Register
VCFG1
ACQT2
USBIF
USBIE
USBIP
CHS3
RCIF
RCIE
RCIP
Bit 5
RA5
RB5
—
—
—
VCFG0
ACQT1
INT0IE
CHS2
TXIE
TXIP
EEIF
EEIE
EEIP
Bit 4
TXIF
RA4
RB4
—
—
—
PCFG3
ACQT0
SSPIF
SSPIE
SSPIP
BCLIE
BCLIP
RE3
BCLIF
channel must be selected and the minimum acquisition
CHS1
the desired location). The appropriate analog input
period is either timed by the user, or an appropriate T
time selected before the Special Event Trigger sets the
GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3)
counter.
RBIE
Bit 3
RA3
RB3
—
—
(3)
PORTE Data Latch Register
TMR0IF
CCP1IF
CCP1IE
CCP1IP
HLVDIF
HLVDIE
HLVDIP
TRISE2
PCFG2
ADCS2
RE2
CHS0
Bit 2
RA2
RB2
(1)
GO/DONE
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TRISE1
PCFG1
ADCS1
INT0IF
RE1
Bit 1
© 2009 Microchip Technology Inc.
RA1
RB1
(1)
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
TRISE0
PCFG0
ADCS0
ADON
RE0
RBIF
Bit 0
RA0
RB0
(1)
on Page:
Values
Reset
21
22
23
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
ACQ