PIC18LF26J13-I/SP Microchip Technology, PIC18LF26J13-I/SP Datasheet - Page 40

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PIC18LF26J13-I/SP

Manufacturer Part Number
PIC18LF26J13-I/SP
Description
28-pin, GP, 64KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18LF26J13-I/SP

Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 2.75 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC18F47J13 FAMILY
REGISTER 3-1:
DS39974A-page 40
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-0
Note 1:
INTSRC
R/W-0
When the CFGPLLEN Configuration bit is used to enable the PLL, clearing OSCTUNE<6> will not disable
the PLL.
INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived directly from INTRC internal oscillator
PLLEN: Frequency Multiplier Enable bit
1 = PLL is enabled
0 = PLL is disabled
TUN<5:0>: Frequency Tuning bits
011111 = Maximum frequency
011110
000001
000000 = Center frequency; oscillator module is running at the calibrated frequency
111111
100000 = Minimum frequency
PLLEN
R/W-0
OSCTUNE: OSCILLATOR TUNING REGISTER (ACCESS F9Bh)
(1)
W = Writable bit
‘1’ = Bit is set
R/W-0
TUN5
R/W-0
TUN4
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
TUN3
R/W-0
TUN2
 2010 Microchip Technology Inc.
x = Bit is unknown
R/W-0
TUN1
R/W-0
TUN0
bit 0

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