PIC18LF45K22-E/MV Microchip Technology, PIC18LF45K22-E/MV Datasheet - Page 314
![32KB, Flash, 1536bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE](/photos/39/71/397183/pic18_sml.jpg)
PIC18LF45K22-E/MV
Manufacturer Part Number
PIC18LF45K22-E/MV
Description
32KB, Flash, 1536bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F26J13-ISS.pdf
(496 pages)
Specifications of PIC18LF45K22-E/MV
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 30x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-UFQFN Exposed Pad
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Number Of Programmable I/os
36
Number Of Timers
3 x 8-bit. 4 x 16-bit
Operating Supply Voltage
1.8 V to 5.5 V
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18(L)F2X/4XK22
REGISTER 18-3:
DS41412D-page 314
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
MC1OUT
R-0
MC1OUT: Mirror Copy of C1OUT bit
MC2OUT: Mirror Copy of C2OUT bit
C1RSEL: Comparator C1 Reference Select bit
1 = FVR BUF1 routed to C1V
0 = DAC routed to C1V
C2RSEL: Comparator C2 Reference Select bit
1 = FVR BUF1 routed to C2V
0 = DAC routed to C2V
C1HYS: Comparator C1 Hysteresis Enable bit
1 = Comparator C1 hysteresis enabled
0 = Comparator C1 hysteresis disabled
C2HYS: Comparator C2 Hysteresis Enable bit
1 = Comparator C2 hysteresis enabled
0 = Comparator C2 hysteresis disabled
C1SYNC: C1 Output Synchronous Mode bit
1 = C1 output is synchronized to rising edge of TMR1 clock (T1CLK)
0 = C1 output is asynchronous
C2SYNC: C2 Output Synchronous Mode bit
1 = C2 output is synchronized to rising edge of TMR1 clock (T1CLK)
0 = C2 output is asynchronous
MC2OUT
R-0
CM2CON1: COMPARATOR 1 AND 2 CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
C1RSEL
R/W-0
REF
REF
input
input
REF
REF
C2RSEL
R/W-0
input
input
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
C1HYS
R/W-0
C2HYS
R/W-0
2010 Microchip Technology Inc.
x = Bit is unknown
C1SYNC
R/W-0
C2SYNC
R/W-0
bit 0
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