PIC18LF46K22-E/MV Microchip Technology, PIC18LF46K22-E/MV Datasheet - Page 221
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PIC18LF46K22-E/MV
Manufacturer Part Number
PIC18LF46K22-E/MV
Description
64KB, Flash, 3968bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F26J13-ISS.pdf
(496 pages)
Specifications of PIC18LF46K22-E/MV
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 30x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-UFQFN Exposed Pad
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
4 KB
Number Of Programmable I/os
36
Number Of Timers
3 x 8-bit. 4 x 16-bit
Operating Supply Voltage
1.8 V to 5.5 V
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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15.4.5 START CONDITION
The I
transition of SDAx from a high-to -low state while
SCLx line is high. A Start condition is always gener-
ated by the master and signifies the transition of the
bus from an Idle to an active state.
shows wave forms for Start and Stop conditions.
A bus collision can occur on a Start condition if the
module samples the SDAx line low before asserting it
low. This does not conform to the I
states no bus collision can occur on a Start.
15.4.6 STOP CONDITION
A Stop condition is a transition of the SDAx line from a
low-to-high state while the SCLx line is high.
FIGURE 15-12:
FIGURE 15-13:
2010 Microchip Technology Inc.
Note: At least one SCLx low time must appear
2
C specification defines a Start condition as a
before a Stop is valid, therefore, if the SDAx
line goes low then high again while the SCLx
line stays high, only the Start condition is
detected.
SDAx
SCLx
I
I
2
2
C™ START AND STOP CONDITIONS
C™ RESTART CONDITION
Condition
Start
S
2
C specification that
Data Allowed
Data Allowed
Figure 15-10
Change of
Change of
Preliminary
Condition
Restart
Sr
15.4.7 RESTART CONDITION
A Restart is valid any time that a Stop would be valid.
A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address. The master may want to address the same or
another slave.
In 10-bit Addressing Slave mode a Restart is required
for the master to clock data out of the addressed slave.
Once a slave has been fully addressed, matching both
high and low address bytes, the master can issue a
Restart and the high address byte with the R/W bit set.
The slave logic will then hold the clock and prepare to
clock out data.
After a full match with R/W clear in 10-bit mode, a prior
match flag is set and maintained. Until a Stop
condition, a high address with R/W clear, or high
address match fails.
15.4.8 START/STOP CONDITION
The SCIE and PCIE bits of the SSPxCON3 register
can enable the generation of an interrupt in Slave
modes that do not typically support this function. Slave
modes where interrupt on Start and Stop detect are
already enabled, these bits will have no effect.
PIC18(L)F2X/4XK22
Data Allowed
Change of
Data Allowed
INTERRUPT MASKING
Change of
Condition
Stop
P
DS41412D-page 221
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