PIC18LF6723T-I/PT Microchip Technology, PIC18LF6723T-I/PT Datasheet - Page 30

• Manufacturer Part Number: PIC18LF6723T-I/PT
• Description: PIC18 With 128KB Flash, 4KB RAM, 1024 DataEE, 12-bit ADC 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6723T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18LF6723T-I/PTTR

PIC18F8723 FAMILY
TABLE 1-3:
DS39894B-page 30
RJ0/ALE
RJ1/OE
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
RJ7/UB
V
V
AV
AV
Legend: TTL = TTL compatible input
Note 1:
SS
DD
SS
DD
RJ0
ALE
RJ1
OE
RJ2
WRL
RJ3
WRH
RJ4
BA0
RJ4
CE
RJ6
LB
RJ7
UB
2:
3:
4:
5:
Pin Name
ST = Schmitt Trigger input with CMOS levels
I
P
Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
Default assignment for ECCP2 in all operating modes (CCP2MX is set).
Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
= Input
= Power
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
12, 32, 48, 71
11, 31, 51, 70
Pin Number
TQFP
62
61
60
59
39
40
41
42
26
25
Type
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
P
P
P
P
Buffer
Type
ST
ST
ST
ST
ST
ST
ST
ST
—
—
—
—
—
—
—
—
—
—
—
—
PORTJ is a bidirectional I/O port.
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
Ground reference for analog modules.
Positive supply for analog modules.
Digital I/O.
External memory address latch enable.
Digital I/O.
External memory output enable.
Digital I/O.
External memory write low control.
Digital I/O.
External memory write high control.
Digital I/O.
External memory byte address 0 control.
Digital I/O
External memory chip enable control.
Digital I/O.
External memory low byte control.
Digital I/O.
External memory high byte control.
CMOS
Analog
O
I
2
C™/SMB = I
= CMOS compatible input or output
= Analog input
= Output
2
Description
C/SMBus input buffer
© 2009 Microchip Technology Inc.