PIC18LF8723T-I/PT Microchip Technology, PIC18LF8723T-I/PT Datasheet - Page 23
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PIC18LF8723T-I/PT
Manufacturer Part Number
PIC18LF8723T-I/PT
Description
PIC18 With 128KB Flash, 4KB RAM, 1024 DataEE, 12-bit ADC 80 TQFP 12x12x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F8627T-IPT.pdf
(44 pages)
2.PIC18F6628-IPT.pdf
(60 pages)
3.PIC18F6628-IPT.pdf
(6 pages)
Specifications of PIC18LF8723T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC18LF8723T-I/PTTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF8723T-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18LF8723T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
3.5
The code sequence detailed in Table 3-5 should be
used, except that the address used in “Step 2” will be in
the range of 000000h to 0007FFh, 000000h to
000FFFh or 000000h to 001FFFh, as defined by the
BBSIZ<1:0> bits in the CONFIG4L register (see
Table 5-1).
TABLE 3-9:
FIGURE 3-9:
© 2009 Microchip Technology Inc.
Step 1: Enable writes and direct access to configuration memory.
Step 2
Note 1:
Command
0000
0000
0000
0000
0000
0000
0000
0000
1111
0000
0000
0000
1111
0000
4-Bit
(1)
Boot Block Programming
: Set Table Pointer for configuration byte to be written. Write even/odd addresses.
Enabling the write protection of Configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of
Configuration bits. Always write all the Configuration bits before enabling the write protection for Configuration
bits.
8E A6
8C A6
0E 30
6E F8
0E 00
6E F7
0E 00
6E F6
<MSB ignored><LSB>
00 00
0E 01
6E F6
<MSB><LSB ignored>
00 00
SET ADDRESS POINTER TO CONFIGURATION LOCATION
Data Payload
CONFIGURATION PROGRAMMING FLOW
Delay P9 and P10
Time for Write
Configuration
Load Even
Program
Address
Done
Start
LSB
BSF
BSF
MOVLW 30h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRL
Load 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
MOVLW 01h
MOVWF TBLPTRL
Load 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
EECON1, EEPGD
EECON1, CFGS
3.6
Unlike code memory, the Configuration bits are
programmed a byte at a time. The Table Write, Begin
Programming 4-bit command (‘1111’) is used, but only
8 bits of the following 16-bit payload will be written. The
LSB of the payload will be written to even addresses and
the MSB will be written to odd addresses. The code
sequence to program two consecutive configuration
locations is shown in Table 3-9.
PIC18F872X FAMILY
Note:
Core Instruction
Configuration Bits Programming
Delay P9 and P10
The address must be explicitly written for
each byte programmed. The addresses
can not be incremented in this mode.
Time for Write
Configuration
Load Odd
Program
Address
Start
MSB
Done
DS39643C-page 23