PIC24F04KA201T-I/SO Microchip Technology, PIC24F04KA201T-I/SO Datasheet - Page 20
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PIC24F04KA201T-I/SO
Manufacturer Part Number
PIC24F04KA201T-I/SO
Description
PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.PIC24F04KA201-ISS.pdf
(8 pages)
2.PIC24F04KA201-ISS.pdf
(48 pages)
3.PIC24F04KA201-ISS.pdf
(224 pages)
4.PIC24F04KA201-ISS.pdf
(26 pages)
Specifications of PIC24F04KA201T-I/SO
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
4KB (1.375K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC24FXXKA2XX
3.10
To verify the code memory, read the code memory
space and compare it with the copy held in the
programmer’s buffer.
process flowchart. Memory reads occur 1 byte at a
time, hence 2 bytes must be read to compare with the
word in the programmer’s buffer. Refer to
“Reading Code Memory”
of reading code memory. On the same lines, the data
EEPROM and Configuration registers can be verified.
FIGURE 3-9:
DS39991A-page 20
Note:
No
Verifying Code Memory and
Configuration Registers
Code
immediately after writing if code protection
is enabled. Since Configuration registers
include the device code protection bit, the
device will not be readable or verifiable if a
device Reset occurs after the code-protect
bits are set (value = 0).
with Post-Increment
with Post-Increment
Set TBLPTR = 0
Read High Byte
Read Low Byte
Word = Expect
code memory
verified?
Data?
Does
Start
End
memory
All
Figure 3-9
VERIFY CODE MEMORY
FLOW
Yes
Yes
for implementation details
should
No
illustrates the verify
Report Error
be
Failure
Section 3.8
verified
3.11
Exit the Program/Verify mode by removing V
MCLR/V
requirement to exit is that an interval of P16 should
elapse between the last clock and the program signals
on PGCx and PGDx before removing V
FIGURE 3-10:
MCLR/V
V
PGDx
PGCx
DD
PP
Exiting ICSP Mode
PP
as illustrated in
PGD = Input
EXITING ICSP™ MODE
2010 Microchip Technology Inc.
V
P16
IH
Figure
V
IH
P17
/V
IHH
3-10. The only
IH
.
IH
from