PIC24F08KA101-E/SS Microchip Technology, PIC24F08KA101-E/SS Datasheet - Page 104
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PIC24F08KA101-E/SS
Manufacturer Part Number
PIC24F08KA101-E/SS
Description
8KB Flash, 1.5KB RAM, 512B EEPROM, 16 MIPS, 18 I/O,16-bit PIC24F Family, NanoWat
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheet
1.MA240017.pdf
(254 pages)
Specifications of PIC24F08KA101-E/SS
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
8KB (2.75K x 24)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP
Processor Series
PIC24F
Core
PIC
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM240001
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC24F16KA102 FAMILY
10.2.2
Idle mode has these features:
• The CPU will stop executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
• If the WDT or FSCM is enabled, the LPRC will
The device will wake from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle, the clock is re-applied to the
CPU and instruction execution begins immediately,
starting with the instruction following the PWRSAV
instruction or the first instruction in the ISR.
10.2.3
Any interrupt that coincides with the execution of a
PWRSAV instruction will be held off until entry into Sleep
or Idle mode has completed. The device will then
wake-up from Sleep or Idle mode.
10.2.4
In PIC24F16KA102 family devices, Deep Sleep mode
is intended to provide the lowest levels of power con-
sumption available without requiring the use of external
switches to completely remove all power from the
device. Entry into Deep Sleep mode is completely
under software control. Exit from Deep Sleep mode can
be triggered from any of the following events:
• POR event
• MCLR event
• RTCC alarm (If the RTCC is present)
• External Interrupt 0
• Deep Sleep Watchdog Timer (DSWDT) time-out
In Deep Sleep mode, it is possible to keep the device
Real-Time Clock and Calendar (RTCC) running without
the loss of clock cycles.
The device has a dedicated Deep Sleep Brown-out
Reset (DSBOR) and a Deep Sleep Watchdog Timer
Reset (DSWDT) for monitoring voltage and time-out
events. The DSBOR and DSWDT are independent of
the standard BOR and WDT used with other
power-managed modes (Sleep, Idle and Doze).
DS39927B-page 102
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 10.4
“Selective Peripheral Module Control”).
also remain active.
IDLE MODE
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
DEEP SLEEP MODE
Preliminary
10.2.4.1
Deep Sleep mode is entered by setting the DSEN bit in
the DSCON register, and then executing a Sleep
command
instruction cycle, to minimize the chance that Deep
Sleep will be spuriously entered.
If the PWRSAV command is not given within one instruc-
tion cycle, the DSEN bit will be cleared by the hardware
and must be set again by the software before entering
Deep Sleep mode. The DSEN bit is also automatically
cleared when exiting the Deep Sleep mode.
The sequence to enter Deep Sleep mode is:
1.
2.
3.
4.
5.
6.
Any time the DSEN bit is set, all bits in the DSWSRC
register will be automatically cleared.
10.2.4.2
Deep Sleep mode exits on any one of the following events:
• POR event on V
• DSWDT time-out. When the DSWDT timer times
• RTCC alarm (if RTCEN = 1).
• Assertion (‘0’) of the MCLR pin.
• Assertion of the INT0 pin (if the interrupt was
circuit to re-arm the V
external V
natural arming voltage of the POR circuit.
out, the device exits Deep Sleep.
enabled before Deep Sleep mode was entered).
The polarity configuration is used to determine the
assertion level (‘0’ or ‘1’) of the pin that will cause
an exit from Deep Sleep mode. Exiting from Deep
Sleep mode requires a change on the INT0 pin
while in Deep Sleep mode.
Note:
If the application requires the Deep Sleep WDT,
enable it and configure its clock source (see
Section 10.2.4.5 “Deep Sleep WDT” for
details).
If the application requires Deep Sleep BOR,
enable it by programming the DSBOREN
Configuration bit (FDS<6>).
If the application requires wake-up from Deep
Sleep on RTCC alarm, enable and configure the
RTCC module (see Section 19.0 “Real-Time
Clock and Calendar (RTCC)” for more
information).
If needed, save any critical application context
data by writing it to the DSGPR0 and DSGPR1
registers (optional).
Enable Deep Sleep mode by setting the DSEN
bit (DSCON<15>).
Enter Deep Sleep mode by issuing 3 NOP
commands, and then a PWRSAV #0 instruction.
To re-enter Deep Sleep after a Deep Sleep
wake-up, allow a delay of at least 3 T
after clearing the RELEASE bit.
(PWRSAV
DD
Entering Deep Sleep Mode
Exiting Deep Sleep Mode
supply must be lowered to the
DD
supply. If there is no DSBOR
#SLEEP_MODE),
DD
© 2009 Microchip Technology Inc.
supply POR circuit, the
within
one
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