PIC24F16KA101T-I/SS Microchip Technology, PIC24F16KA101T-I/SS Datasheet - Page 16
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PIC24F16KA101T-I/SS
Manufacturer Part Number
PIC24F16KA101T-I/SS
Description
16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 16 I/O,16-bit PIC24F Family, NanoWatt
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.MA240017.pdf
(254 pages)
2.PIC24F04KA201-ISS.pdf
(48 pages)
3.PIC24F16KA101-ISS.pdf
(18 pages)
Specifications of PIC24F16KA101T-I/SS
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
16KB (5.5K x 24)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24F16KA101T-I/SS
Manufacturer:
MICROCHIR
Quantity:
20 000
PIC24FXXKAXXX
3.8
The procedure for writing the Configuration registers is
the same as for writing code memory. The only differ-
ence is that, only one word is programmed in each
operation. When writing Configuration registers, one
word is programmed during each operation, only work-
ing register, W0, is used as a temporary holding
register for the data to be programmed.
Table 3-7
Configuration registers.
Table 3-7 provides the ICSP programming details for
programming the Configuration registers, including the
serial pattern with the ICSP command code, which
must be transmitted LSB first using the PGCx and
PGDx pins (see Figure 3-2). In Step 1 of Table 3-8, the
Reset vector is exited. In Step 2, the NVMCON register
is initialized for programming code memory. In Step 3,
the 24-bit starting destination address for programming
is loaded into the TBLPAG register and W7 register.
DS39919A-page 16
Note:
Note:
Writing Configuration Registers
provides
The TBLPAG register is hard-coded to
0xF8 (the upper byte address of all
locations of the Configuration registers).
The TBLPAG register must be loaded with
F8h.
the
default
values
Advance Information
of
the
TABLE 3-7:
FBS
FGS
FOSCSEL
FOSC
FWDT
FPOR
FICD
FDS
Note 1:
Configuration
(3)
Registers
(4)
(2,3)
(1)
2:
3:
4:
The I2C2SEL bit (FPOR<4>) is not
implemented on PIC24FXXKAX01 and
PIC24FXXKAX00 devices and should be
programmed as ‘1’.
The FICD<6> bit is a reserved bit and
should be programmed as ‘1’.
The Configuration registers, FBS and
FICD, are reserved locations on
PIC24F04KA2XX devices, and should be
programmed with the default value given
above.
The RTCSOSC bit (FDS<5>) is not
implemented on PIC24F04KA2XX
devices, and should be programmed
as ‘1’.
DEFAULT VALUES FOR
CONFIGURATION REGISTER
SERIAL INSTRUCTION
© 2008 Microchip Technology Inc.
Value
DFh
FBh
C3h
0Fh
FFh
FFh
03h
87h