PIC24FJ16MC101-I/P Microchip Technology, PIC24FJ16MC101-I/P Datasheet - Page 157
PIC24FJ16MC101-I/P
Manufacturer Part Number
PIC24FJ16MC101-I/P
Description
16-bit Motor Control Family, 16 MIPS, 16KB Flash, 1KB RAM 20 PDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheet
1.PIC24FJ16MC101-IP.pdf
(304 pages)
Specifications of PIC24FJ16MC101-I/P
Featured Product
PIC24FJ/33FJ MCUs & dsPIC® DSCs
Core Processor
PIC
Core Size
16-Bit
Speed
16 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
16KB (5.5K x 24)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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REGISTER 16-3:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-2
bit 1
bit 0
FRMEN
R/W-0
U-0
—
FRMEN: Framed SPIx Support bit
1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output)
0 = Framed SPIx support disabled
SPIFSD: Frame Sync Pulse Direction Control bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
FRMPOL: Frame Sync Pulse Polarity bit
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
Unimplemented: Read as ‘0’
FRMDLY: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with first bit clock
0 = Frame sync pulse precedes first bit clock
Unimplemented: This bit must not be set to ‘1’ by the user application.
SPIFSD
R/W-0
U-0
—
SPIxCON2: SPIx CONTROL REGISTER 2
‘1’ = Bit is set
W = Writable bit
FRMPOL
R/W-0
U-0
—
U-0
U-0
Preliminary
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
PIC24FJ16MC101/102
U-0
U-0
—
—
x = Bit is unknown
FRMDLY
R/W-0
U-0
—
DS39997B-page 157
U-0
U-0
—
—
bit 8
bit 0
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