PIC24FJ256DA210T-I/BG Microchip Technology, PIC24FJ256DA210T-I/BG Datasheet - Page 335

• Manufacturer Part Number: PIC24FJ256DA210T-I/BG
• Description: 16-bit, 256KB Flash, 96K RAM, USB, Graphics 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256DA210T-I/BG

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.0
The triple comparator module provides three dual input
comparators. The inputs to the comparator can be
configured to use any one of five external analog inputs
(CxINA, CxINB, CxINC, CxIND and V
voltage reference input from one of the internal band
gap references or the comparator voltage reference
generator (V
FIGURE 24-1:
 2010 Microchip Technology Inc.
Note:
Note 1: Refer Register 25-1 for bit details.
CCH<1:0>
C
C
C
V
V
V
V
CVREFM<1:0>
C
V
CV
CVREFP
CREF
BG
BG
BG
REF
REF
X
X
X
X
TRIPLE COMPARATOR
MODULE
INB
INC
IND
INA
REF
/2
/6
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
associated “PIC24F Family Reference
Manual”.
+
+
BG,
(1)
V
BG
/2, V
(1)
TRIPLE COMPARATOR MODULE BLOCK DIAGRAM
00
10
11
01
0
BG/6 and CV
1
Select
Logic
Input
00
01
10
11
0
1
REF
+
-
).
V
V
V
V
V
V
IN
IN
REF
IN
IN
IN
IN
-
+
-
+
-
+
+) and a
C1
C2
PIC24FJ256DA210 FAMILY
C3
EVPOL<1:0>
EVPOL<1:0>
CPOL
EVPOL<1:0>
CPOL
CPOL
The comparator outputs may be directly connected to
the CxOUT pins. When the respective COE equals ‘1’,
the I/O pad logic makes the unsynchronized output of
the comparator available on the pin.
A simplified block diagram of the module in shown in
Figure 24-1. Diagrams of the possible individual
comparator configurations are shown in Figure 24-2.
Each comparator has its own control register,
CMxCON (Register 24-1), for enabling and configuring
its operation. The output and event status of all three
comparators is provided in the CMSTAT register
(Register 24-2).
Trigger/Interrupt
Trigger/Interrupt
Trigger/Interrupt
Logic
Logic
Logic
COE
COE
COE
CEVT
CEVT
COUT
CEVT
COUT
COUT
DS39969B-page 335
C1OUT
C2OUT
C3OUT
Pin
Pin
Pin