PIC24FJ48GA002-I/ML Microchip Technology, PIC24FJ48GA002-I/ML Datasheet - Page 32
![16-bit Family, 16 MIPS, 48KB Flash, 8192 Bytes RAM, 21 I/O, NanoWatt 28 QFN 6x6m](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC24FJ48GA002-I/ML
Manufacturer Part Number
PIC24FJ48GA002-I/ML
Description
16-bit Family, 16 MIPS, 48KB Flash, 8192 Bytes RAM, 21 I/O, NanoWatt 28 QFN 6x6m
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ16GA002-ISS.pdf
(268 pages)
3.PIC24FJ16GA002-ISS.pdf
(22 pages)
Specifications of PIC24FJ48GA002-I/ML
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DV164033, MA240013, DM300027, AC164127, DM240002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24FJ48GA002-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC24FJXXXGA0XX
4.6.2
Configuration bits may be programmed a single byte at
a time using the PROGW command. This command
specifies the configuration data and Configuration
register
programmed, any unimplemented or reserved bits
must be programmed with a ‘1’.
Two PROGW commands are required to program the
Configuration bits. A flowchart for Configuration bit
programming is shown in Figure 4-5.
4.6.3
After the Configuration bits are programmed, the
contents of memory should be verified to ensure that
the programming was successful. Verification requires
the Configuration bits to be read back and compared
against the copy held in the programmer’s buffer. The
READP command reads back the programmed
Configuration bits and verifies that the programming
was successful.
DS39768D-page 32
Note:
address.
PROGRAMMING METHODOLOGY
If the General Segment Code-Protect bit
(GCP) is programmed to ‘0’, code memory
is code-protected and can not be read.
Code memory must be verified before
enabling read protection. See Section 4.6.4
“Code-Protect Configuration Bits” for
more
Configuration bits.
PROGRAMMING VERIFICATION
information
When
Configuration
about
code-protect
bits
are
prevents code memory from being read (read protection).
4.6.4
CW1 Configuration register controls code protection for
the PIC24FJXXXGA0XX family. Two forms of code pro-
tection are provided. One form prevents code memory
from being written (write protection) and the other
GWRP (CW1<12>) controls write protection and GCP
(CW1<13>) controls read protection. Protection is
enabled when the respective bit is ‘0’.
Erasing sets GWRP and GCP to ‘1’, which allows the
device to be programmed.
When write protection is enabled (GWRP = 0), any
programming operation to code memory will fail.
When read protection is enabled (GCP = 0), any read
from code memory will cause a 0h to be read, regard-
less of the actual contents of code memory. Since the
programming executive always verifies what it
programs, attempting to program code memory with
read protection enabled also will result in failure.
It is imperative that both GWRP and GCP are ‘1’ while
the device is being programmed and verified. Only after
the device is programmed and verified should either
GWRP or GCP be programmed to ‘0’ (see Section 4.6
“Configuration Bits Programming”).
Note:
CODE-PROTECT
CONFIGURATION BITS
Bulk Erasing in ICSP mode is the only way
to reprogram code-protect bits from an ON
state (‘0’) to an Off state (‘1’).
© 2008 Microchip Technology Inc.