PIC24FJ48GA004T-I/ML Microchip Technology, PIC24FJ48GA004T-I/ML Datasheet - Page 31
![16-bit Family, 16 MIPS, 48KB Flash, 8192 Bytes RAM, 35 I/O, NanoWatt 44 QFN 8x8x](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC24FJ48GA004T-I/ML
Manufacturer Part Number
PIC24FJ48GA004T-I/ML
Description
16-bit Family, 16 MIPS, 48KB Flash, 8192 Bytes RAM, 35 I/O, NanoWatt 44 QFN 8x8x
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ16GA002-ISS.pdf
(268 pages)
3.PIC24FJ16GA002-ISS.pdf
(22 pages)
Specifications of PIC24FJ48GA004T-I/ML
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
TABLE 4-2:
© 2008 Microchip Technology Inc.
ICS
IESO
IOL1WAY
JTAGEN
OSCIOFNC
SOSCSEL1:
SOSCSEL0
POSCMD1:
POSCMD0
WDTPOST3:
WDTPOST0
WDTPRE
WINDIS
WUTSEL1:
WUTSEL0
Note 1:
(1)
Bit Field
2:
(1)
(2)
Available on 28 and 44-pin packages only.
Available only on 28 and 44-pin devices with a silicon revision of 3042h or higher.
(2)
PIC24FJXXXGA0XX FAMILY CONFIGURATION BITS DESCRIPTION (CONTINUED)
CW2<12:11>
CW2<14:13>
CW2<1:0>
CW1<3:0>
CW2<15>
CW1<14>
Register
CW1<8>
CW2<4>
CW2<5>
CW1<4>
CW1<6>
ICD Pin Placement Select bit
11 = ICD EMUC/EMUD pins are shared with PGC1/PGD1
10 = ICD EMUC/EMUD pins are shared with PGC2/PGD2
01 = ICD EMUC/EMUD pins are shared with PGC3/PGD3
00 = Reserved; do not use
Internal External Switchover bit
1 = Two-Speed Start-up enabled
0 = Two-Speed Start-up disabled
IOLOCK Bit One-Way Set Enable bit
0 = The OSCCON<IOLOCK> bit can be set and cleared as needed (provided
1 = The OSCCON<IOLOCK> bit can only be set once (provided an unlocking
JTAG Enable bit
1 = JTAG enabled
0 = JTAG disabled
OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is clock output
0 = OSC2 is general purpose digital I/O pin
Secondary Oscillator Power Mode Select bits
11 = Default (high drive strength) mode
01 = Low-Power (low drive strength) mode
x0 = Reserved; do not use
Primary Oscillator Mode Select bits
11 = Primary oscillator disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
Watchdog Timer Prescaler bit
1111 = 1:32,768
1110 = 1:16,384
0001 = 1:2
0000 = 1:1
Watchdog Timer Postscaler bit
1 = 1:128
0 = 1:32
Windowed WDT bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode; FWDTEN must be ‘1’
Voltage Regulator Standby Mode Wake-up Time Select bits
11 = Default regulator wake time used
01 = Fast regulator wake time used
x0 = Reserved; do not use
.
.
.
an unlocking sequence is executed)
sequence is executed). Once IOLOCK is set, this prevents any possible
future RP register changes
PIC24FJXXXGA0XX
Description
DS39768D-page 31